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H. Momose

Also published under: H. S. Momose, Hisayo S. Momose, Hisayo Sasaki Momose

Publications
115
Citations
1,650
Publications by Year
19802019
Co-Authors:
Show All Co-Authors (200)
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H. Momose

Also published under: H. S. Momose, Hisayo S. Momose, Hisayo Sasaki Momose

Affiliation

Nishizawa Electric Meters Manufacturing Co.
Ltd
Sakaki 6249, Sakaki-cho, Hanishina-gun, Nagano, Japan

Publication Topics

Biography

Hisayo Sasaki Momose received the Ph.D. degree in electrical engineering from the Tokyo Institute of Technology, Tokyo, Japan.,She is currently with the Center for Semiconductor Research and Development, Toshiba Corporation, Kawasaki, Japan. Her current research interests include noise characteristics and the related issues of CMOS imaging devices.(Based on document published on 11 November 2014).
Publications
115
Citations
1,650
Publications by Year
19802019
Co-Authors:
Show All Co-Authors (200)
Author's Published Works

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A CMOS Integrated Sweat Monitoring System for Medical Applications

T. Sakata;Y. Mitani;K. Miyaji;S. Kaneko;T. Uekura;H. Taki;H. Momose;K. Johguchi

2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS)
Year: 2019 | Conference Paper |
Cited by: Papers (1)
Recently, demand for sweat measuring sensors has been increasing, especially for detection of heat stroke, dehydration and pathology of neurological diseases. Currently commercially available sensors are immobile, as they are large and require cables and hoses. Previous studies have presented a design that combines a custom chip analog to digital converter (ADC), discrete capacitive humidity and t...Show More

A CMOS Integrated Sweat Monitoring System for Medical Applications

T. Sakata;Y. Mitani;K. Miyaji;S. Kaneko;T. Uekura;H. Taki;H. Momose;K. Johguchi

Year: 2019 | Conference Paper |

Unified Transient and Frequency Domain Noise Simulation for Random Telegraph Noise and Flicker Noise Using a Physics-Based Model

Yusuke Higashi;Nobuyuki Momo;Hiroki Sasaki;Hisayo Sasaki Momose;Tatsuya Ohguro;Yuichiro Mitani;Takamitsu Ishihara;Kazuya Matsuzawa

IEEE Transactions on Electron Devices
Year: 2014 | Volume: 61, Issue: 12 | Journal Article |
Cited by: Papers (15)
Unified transient and frequency domain noise simulation of random telegraph noise and flicker noise is conducted using a multiphonon-assisted model that considers tunneling probabilities and energy transitions of discretized traps in the gate insulator of MOSFETs. The proposed model is able to concurrently represent the dynamic behavior of electron and hole trapping and detrapping via interactions...Show More

Unified Transient and Frequency Domain Noise Simulation for Random Telegraph Noise and Flicker Noise Using a Physics-Based Model

Yusuke Higashi;Nobuyuki Momo;Hiroki Sasaki;Hisayo Sasaki Momose;Tatsuya Ohguro;Yuichiro Mitani;Takamitsu Ishihara;Kazuya Matsuzawa

Year: 2014 | Volume: 61, Issue: 12 | Journal Article |

Comprehensive understanding of random telegraph noise with

Y. Higashi;N. Momo;H. S. Momose;T. Ohguro;K. Matsuzawa

2011 Symposium on VLSI Technology - Digest of Technical Papers
Year: 2011 | Conference Paper |
Physical modeling of transient and frequency domain noise simulation for random telegraph noise (RTN) is conducted, considering discretized traps and energy transition in insulator. The models are implemented in a 3D device simulator to consider the device structure effect and bias effect universally. Trap density and trap distribution in insulator are predicted quantitatively with comparison of m...Show More

Comprehensive understanding of random telegraph noise with

Y. Higashi;N. Momo;H. S. Momose;T. Ohguro;K. Matsuzawa

Year: 2011 | Conference Paper |

Analysis of Fin width and temperature dependence of flicker noise for bulk-FinFET

T. Ohguro;K. Okano;T. Izumida;S. Inaba;N. Momo;K. Kokubun;H. S. Momose;Y. Toyoshima

2009 European Microwave Integrated Circuits Conference (EuMIC)
Year: 2009 | Conference Paper |
Cited by: Papers (1)
In this paper, detailed analysis of Fin width and temperature dependence of flicker noise for bulk-FinFET are described. The FinFET with narrow fin width such as below 30 nm is attractive for scaled CMOS because of double gate structure. Additionally, the flicker noise of FinFET decreases and the temperature dependence of the noise become smaller as the fin width becomes narrower. According to our...Show More

Analysis of Fin width and temperature dependence of flicker noise for bulk-FinFET

T. Ohguro;K. Okano;T. Izumida;S. Inaba;N. Momo;K. Kokubun;H. S. Momose;Y. Toyoshima

Year: 2009 | Conference Paper |

90nm node RF CMOS technology with latch-up immunity on high-resistivity substrate

N. Momo;Y. Higashi;M. Oda;K. Matsuzawa;K. Kokubun;T. Ohguro;H. S. Momose;Y. Toyoshima

2009 European Microwave Integrated Circuits Conference (EuMIC)
Year: 2009 | Conference Paper |
Cited by: Papers (1)
This paper presents a detailed analysis of latch-up characteristics for 90 nm RF CMOS on high-resistivity substrate with 400 ohm-cm for the first time. According to our measurement and simulation results, latch-up dependence of PNP base and NPN emitter injection mode on Si substrate resistivity is small. On the other hand, PNP emitter and NPN base injection modes are sensitive to the resistivity b...Show More

90nm node RF CMOS technology with latch-up immunity on high-resistivity substrate

N. Momo;Y. Higashi;M. Oda;K. Matsuzawa;K. Kokubun;T. Ohguro;H. S. Momose;Y. Toyoshima

Year: 2009 | Conference Paper |

Influence of surface orientation on electrical characteristics in MOSFETs with slightly tilted off-axis channel

Hisayo S. Momose

2008 9th International Conference on Solid-State and Integrated-Circuit Technology
Year: 2008 | Conference Paper |
Si surface properties and electrical characteristics in n- and p-MOSFETs with 2 - 6 degree tilted off-axis (110) channel were reported. The transconductance of p-MOSFET with off-axis channel was significantly degraded compared with that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved compared with that of normal channel. The changes were larger than those observed ...Show More

Influence of surface orientation on electrical characteristics in MOSFETs with slightly tilted off-axis channel

Hisayo S. Momose

Year: 2008 | Conference Paper |

Process dependence of 0.11 μm RF CMOS on high-resistivity substrate for System on Chip (SOC) application

T. Ohguro;K. Kojima;N. Momo;H. S. Momose;Y. Toyoshima

2008 IEEE Radio Frequency Integrated Circuits Symposium
Year: 2008 | Conference Paper |
Cited by: Papers (1)
High-resistivity substrate with beyond 1000 ohm-cm realizes high performance in terms of inductor, antenna, MIM capacitor and substrate noise for high- frequency applications. However, this wafer has serious problems for mixed-signal, RF and digital circuits. Those are reduction of high resistivity during sinter process such as 400degC, larger leakage current between nwells, extreme lower snap-bac...Show More

Process dependence of 0.11 μm RF CMOS on high-resistivity substrate for System on Chip (SOC) application

T. Ohguro;K. Kojima;N. Momo;H. S. Momose;Y. Toyoshima

Year: 2008 | Conference Paper |

Effects of Si channel orientation on MOSFET characteristics

Hisayo S. Momose;Sadayuki Yoshitomi

2008 26th International Conference on Microelectronics
Year: 2008 | Conference Paper |
Cited by: Papers (4)
The Si channel surface orientation dependence of electrical characteristics in ultra-thin EOT gate MOSFETs was reviewed. The excellent DC and RF performance were obtained in ultra-thin SiO2 gate p-MOSFETs with (110) oriented Si channel. The properties and electrical characteristics in n- and p-MOSFETs with 2 – 6 degree tilted off-axis (110) channel were also reported. The transconductance of p-MOS...Show More

Effects of Si channel orientation on MOSFET characteristics

Hisayo S. Momose;Sadayuki Yoshitomi

Year: 2008 | Conference Paper |

Electrical Characteristics in N- and P-MOSFETS with Slightly Tilted Off-Axis (110) Channel

H. S. Momose;S. Yoshitomi;K. Kojima;T. Ohguro;Y. Toyoshima;H. Ishiuchi

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems
Year: 2007 | Conference Paper |
Cited by: Papers (2)
Si surface properties and electrical characteristics in n- and p-MOSFETs with 2-6 degree tilted off-axis (110) channel were investigated for the first time. The transconductance of p-MOSFET with off-axis channel was significantly degraded than that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved than that of normal channel. The changes were larger than those observ...Show More

Electrical Characteristics in N- and P-MOSFETS with Slightly Tilted Off-Axis (110) Channel

H. S. Momose;S. Yoshitomi;K. Kojima;T. Ohguro;Y. Toyoshima;H. Ishiuchi

Year: 2007 | Conference Paper |

Analysis of 1/f noise for CMOS with high-k gate dielectrics

T. Ohguro;K. Kojima;R Iijima;T. Watanabe;M Takayanagi;H.S. Momose;K. Ishimaru;H. Ishiuchi

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings
Year: 2006 | Conference Paper |
HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, the authors discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict...Show More

Analysis of 1/f noise for CMOS with high-k gate dielectrics

T. Ohguro;K. Kojima;R Iijima;T. Watanabe;M Takayanagi;H.S. Momose;K. Ishimaru;H. Ishiuchi

Year: 2006 | Conference Paper |

HfSiON gate dielectrics design for mixed signal CMOS

K. Kojima;R. Iijima;T. Ohguro;T. Watanabe;M. Takayanagi;H.S. Momose;K. Tshimaru;H. Ishiuchi

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005.
Year: 2005 | Conference Paper |
Cited by: Papers (5)
HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported by T. Watanabe et al in 2004. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, we discuss 1/f noise and matching of CMOS with HfSiON gate die...Show More

HfSiON gate dielectrics design for mixed signal CMOS

K. Kojima;R. Iijima;T. Ohguro;T. Watanabe;M. Takayanagi;H.S. Momose;K. Tshimaru;H. Ishiuchi

Year: 2005 | Conference Paper |

The impact of oxynitride process, deuterium annealing and STI stress to1/f noise of 0.11 /spl mu/m CMOS

T. Ohguro;Y. Okayama;K. Matsuzawa;K. Matsunaga;N. Aoki;K. Kojima;H.S. Momose;K. Ishimaru

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407)
Year: 2003 | Conference Paper |
Cited by: Papers (6) | Patents (3)
In this paper, it is shown that the 1/f noise is improved by plasma nitridation instead of NO annealing and deuterium annealing after metal formation. Additionally, dependence of the noise on distance between gate electrode and STI edge is reported for the first time.Show More

The impact of oxynitride process, deuterium annealing and STI stress to1/f noise of 0.11 /spl mu/m CMOS

T. Ohguro;Y. Okayama;K. Matsuzawa;K. Matsunaga;N. Aoki;K. Kojima;H.S. Momose;K. Ishimaru

Year: 2003 | Conference Paper |

1.5-nm gate oxide CMOS on [110] surface-oriented Si substrate

H.S. Momose;T. Ohguro;K. Kojima;S. Nakamura;Y. Toyoshima

IEEE Transactions on Electron Devices
Year: 2003 | Volume: 50, Issue: 4 | Journal Article |
The dc and RF analog characteristics of ultrathin gate oxide CMOS on [110] surface-oriented Si substrates were investigated for the first time. The transconductance of p-MOSFETs on [110] substrates is 1.9 times greater than that on [100] substrates even in gate oxides in the direct-tunneling regime. An extremely high cutoff frequency of 110 GHz was obtained in 0.11 /spl mu/m gate length p-MOSFETs ...Show More

1.5-nm gate oxide CMOS on [110] surface-oriented Si substrate

H.S. Momose;T. Ohguro;K. Kojima;S. Nakamura;Y. Toyoshima

Year: 2003 | Volume: 50, Issue: 4 | Journal Article |

Ultrathin gate oxide CMOS on [111] surface-oriented Si substrate

H.S. Momose;T. Ohguro;S.-I. Nakamura;Y. Toyoshima;H. Ishiuchi;H. Iwai

IEEE Transactions on Electron Devices
Year: 2002 | Volume: 49, Issue: 9 | Journal Article |
The properties of ultrathin gate oxides in the direct-tunneling regime and the characteristics of the related CMOS transistors on a [111] surface-oriented Si substrate were investigated and compared with those on a [100] substrate for the first time. It was confirmed that low field mobility of n-MOSFETs on the [111] substrate is smaller than that on the [100] substrate and that of p-MOSFETs on [11...Show More

Ultrathin gate oxide CMOS on [111] surface-oriented Si substrate

H.S. Momose;T. Ohguro;S.-I. Nakamura;Y. Toyoshima;H. Ishiuchi;H. Iwai

Year: 2002 | Volume: 49, Issue: 9 | Journal Article |

110 GHz cutoff frequency of ultra-thin gate oxide p-MOSFETs on [110] surface-oriented Si substrate

H.S. Momose;T. Ohguro;K. Kojima;S. Nakamura;Y. Toyoshima

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)
Year: 2002 | Conference Paper |
The DC and RF analog characteristics of ultra-thin gate oxide CMOS on [110] surface-oriented Si substrate were investigated for the first time. Gm of p-MOSFET on [110] substrate is 1.9 times greater than that on [100] substrate, even in gate oxides in a direct-tunneling regime. An extremely high cut-off frequency of 110 GHz was obtained in 0.11 /spl mu/m gate length p-MOSFET with 1.5 nm gate oxide...Show More

110 GHz cutoff frequency of ultra-thin gate oxide p-MOSFETs on [110] surface-oriented Si substrate

H.S. Momose;T. Ohguro;K. Kojima;S. Nakamura;Y. Toyoshima

Year: 2002 | Conference Paper |

Improvement of high resistivity substrate for future mixed analog-digital applications

T. Ohguro;K. Kojima;H.S. Momose;S. Nitta;T. Fukuda;T. Enda;Y. Toyoshima

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)
Year: 2002 | Conference Paper |
Fully oxygen precipitated (FOP) wafers can suppress slip generation during the STI process and maintain high substrate resistivity. Additional boron implantation can suppress the leakage current between the adjacent wells due to shallow Xj. No effect on MOSFET characteristics by this implantation was observed. The high resistivity substrate (HRS) can provide good ESD performance and suppress the p...Show More

Improvement of high resistivity substrate for future mixed analog-digital applications

T. Ohguro;K. Kojima;H.S. Momose;S. Nitta;T. Fukuda;T. Enda;Y. Toyoshima

Year: 2002 | Conference Paper |

A study of analog characteristics of CMOS with heavily nitrided NO oxynitrides

T. Ohguro;T. Nagano;M. Fujiwara;M. Takayanagi;T. Shimizu;H.S. Momose;S. Nakamura;Y. Toyoshima

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)
Year: 2001 | Conference Paper |
Cited by: Papers (8) | Patents (4)
Recently, heavily nitrided NO oxynitride has been proposed as an alternative to pure oxide in order to realize high drivability and suppress a large gate leakage current (Fujiwara et al, Digest of IEDM 2000, pp. 227-30, 2000). However, in general, oxynitride has higher interface state density than that of pure oxide, and brings low frequency noise (or 1/f noise) degradation (Kimijima et al., 1999)...Show More

A study of analog characteristics of CMOS with heavily nitrided NO oxynitrides

T. Ohguro;T. Nagano;M. Fujiwara;M. Takayanagi;T. Shimizu;H.S. Momose;S. Nakamura;Y. Toyoshima

Year: 2001 | Conference Paper |

Study of wafer orientation dependence on performance and reliability of CMOS with direct-tunneling gate oxide

H.S. Momose;T. Ohguro;S. Nakamura;Y. Toyoshima;H. Ishiuchi;H. Iwai

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)
Year: 2001 | Conference Paper |
Cited by: Papers (8)
With the expected limitations of conventional CMOS downsizing, various new structures, such as vertical and concave MOSFETs, are under serious investigation. These new types of MOSFETs have a special feature in that the channel of the MOSFETs consists of various surfaces with different crystal orientations. With thinning of the gate oxides, the substrate orientation dependence of the oxide quality...Show More

Study of wafer orientation dependence on performance and reliability of CMOS with direct-tunneling gate oxide

H.S. Momose;T. Ohguro;S. Nakamura;Y. Toyoshima;H. Ishiuchi;H. Iwai

Year: 2001 | Conference Paper |

Ultrathin gate oxide CMOS with nondoped selective epitaxial Si channel layer

H.S. Momose;T. Ohguro;E. Morifuji;H. Sugaya;S. Nakamura;H. Iwai

IEEE Transactions on Electron Devices
Year: 2001 | Volume: 48, Issue: 6 | Journal Article |
Cited by: Papers (6)
The nondoped selective epitaxial Si channel technique has been applied to ultrathin gate oxide CMOS transistors. It was confirmed that drain current drive and transconductance are improved in the epitaxial channel MOSFETs with ultrathin gate oxides in the direct-tunneling regime. It was also found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current. The relat...Show More

Ultrathin gate oxide CMOS with nondoped selective epitaxial Si channel layer

H.S. Momose;T. Ohguro;E. Morifuji;H. Sugaya;S. Nakamura;H. Iwai

Year: 2001 | Volume: 48, Issue: 6 | Journal Article |

Cutoff frequency and propagation delay time of 1.5-nm gate oxide CMOS

H.S. Momose;E. Morifuji;T. Yoshitomi;T. Ohguro;M. Saito;H. Iwai

IEEE Transactions on Electron Devices
Year: 2001 | Volume: 48, Issue: 6 | Journal Article |
Cited by: Papers (37)
The high-frequency AC characteristics of 1.5-nm direct-tunneling gate SiO/sub 2/ CMOS are described. Very high cutoff frequencies of 170 GHz and 235 GHz were obtained for 0.08-/spl mu/m and 0.06-/spl mu/m gate length nMOSFETs at room temperature. Cutoff frequency of 65 GHz was obtained for 0.15-/spl mu/m gate length pMOSFETs using 1.5-nm gate SiO/sub 2/ for the first time. The normal oscillations ...Show More

Cutoff frequency and propagation delay time of 1.5-nm gate oxide CMOS

H.S. Momose;E. Morifuji;T. Yoshitomi;T. Ohguro;M. Saito;H. Iwai

Year: 2001 | Volume: 48, Issue: 6 | Journal Article |

Power Si-MOSFET operating with high efficiency under low supply voltage

T. Ohguro;M. Saito;E. Morifuji;K. Murakami;K. Matsuzaki;T. Yoshitomi;T. Morimoto;H.S. Momose;Y. Katsumata;H. Iwai

IEEE Transactions on Electron Devices
Year: 2000 | Volume: 47, Issue: 12 | Journal Article |
Cited by: Papers (3)
A design method for RF power Si-MOSFETs suitable for low-voltage operation with high power-added efficiency is presented. In our experiments, supply voltages from 1 V to 3 V are examined. As the supply voltage is decreased, degradation of transconductance also takes place. However, this problem is overcome, even at extremely low supply voltages, by adopting a short gate length and also increasing ...Show More

Power Si-MOSFET operating with high efficiency under low supply voltage

T. Ohguro;M. Saito;E. Morifuji;K. Murakami;K. Matsuzaki;T. Yoshitomi;T. Morimoto;H.S. Momose;Y. Katsumata;H. Iwai

Year: 2000 | Volume: 47, Issue: 12 | Journal Article |

An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs

Jung-Suk Goo;Chang-Hoon Choi;F. Danneville;E. Morifuji;H.S. Momose;Zhiping Yu;H. Iwai;T.H. Lee;R.W. Dutton

IEEE Transactions on Electron Devices
Year: 2000 | Volume: 47, Issue: 12 | Journal Article |
Based on an active transmission line concept and two-dimensional (2-D) device simulations, an accurate and computationally efficient simulation technique for high frequency noise performance of MOSFETs is demonstrated. Using a Langevin stochastic source term model and small-signal equivalent circuit of the MOSFET, three intrinsic noise parameters (/spl gamma/, /spl delta/, and c) for the drain noi...Show More

An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs

Jung-Suk Goo;Chang-Hoon Choi;F. Danneville;E. Morifuji;H.S. Momose;Zhiping Yu;H. Iwai;T.H. Lee;R.W. Dutton

Year: 2000 | Volume: 47, Issue: 12 | Journal Article |

Thermal stability of CoSi/sub 2/ film for CMOS salicide

T. Ohguro;M. Saito;E. Morifuji;T. Yoshitomi;T. Morimoto;H.S. Momose;Y. Katsumata;H. Iwai

IEEE Transactions on Electron Devices
Year: 2000 | Volume: 47, Issue: 11 | Journal Article |
Cited by: Papers (26)
We describe the relationship between the sheet resistance of Co-silicided poly-Si and various doping elements. The surface condition of the poly-Si before Co sputtering plays an important role in suppressing the "narrow line effect," in which the silicide sheet resistance degrades as the gate length decreases. Si-O and Si-C bonding takes place in the gate poly-Si during RIE processing for gate sid...Show More

Thermal stability of CoSi/sub 2/ film for CMOS salicide

T. Ohguro;M. Saito;E. Morifuji;T. Yoshitomi;T. Morimoto;H.S. Momose;Y. Katsumata;H. Iwai

Year: 2000 | Volume: 47, Issue: 11 | Journal Article |

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