I. Introduction
For high-speed logic applications, in order to realize high performance despite a low supply voltage, MOSFET scaling has been achieved continuously by means of various modifications in the scaling rules. Since the beginning of the 1990s, in view of the expected limitation of conventional CMOS downsizing, various new types of three-dimensional MOSFETs have been proposed [1]–[2]. These new types of MOSFETs have special features in the channel, which consists of various Si surfaces with different crystal orientations. It is known that channel carrier mobility is strongly dependent on Si surface orientation [3]–[4]. Considering the introduction of both n and p-MOSFETs with vertical channel, it is possible to select the best surface for n-and p-MOSFETs separately [5]–[6]. Recently, CMOS with (100) channel n-MOSFETs and (110) channel p-MOSFETs has begun to be used for high-end microprocessor products [7].