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Ratul Kr Baruah - IEEE Xplore Author Profile
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Ratul Kr Baruah

Also published under: Ratul Kumar Baruah, Ratul K. Baruah

Publications
23
Citations
188
Publications by Year
20092024
Co-Authors:
Show All Co-Authors (21)
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Ratul Kr Baruah

Also published under: Ratul Kumar Baruah, Ratul K. Baruah

Affiliation

Department of ECE
Tezpur University
Tezpur, Assam, India

Publication Topics

Biography

Ratul K. Baruah (Senior Member, IEEE) received the Ph.D. degree from the Department of Electronics and Electrical engineering, Indian Institute of Technology at Guwahati, Guwahati, India, in 2015.,He holds an Associate Professorship at the Department of Electronics and Communication Engineering, Tezpur University, Tezpur, Assam, India. He was a Visiting Post-Doctoral Fellow at the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA, from 2018 to 2019. He works on semiconductor devices, biosensors, and flexible electronics.(Based on document published on 6 June 2024).
Publications
23
Citations
188
Publications by Year
20092024
Co-Authors:
Show All Co-Authors (21)
Author's Published Works

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Lateral Straggle Based Interface Trap Sensitivity in n-p-n SOI Double Gate TFETs

Deepjyoti Deb;Saurav Nath;Prachuryya Subash Das;Ratul Kr Baruah;Rupam Goswami

2024 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)
Year: 2024 | Conference Paper |
This article reports the impact of interface traps and dopant lateral straggle on a tunnel field-effect transistor (TFET) based on an n-p-n silicon body with a double-gate structure. Both gates are on the same side, spanning over two p-n junctions. In the proposed device, interface trap analysis is conducted considering a constant doping profile and an analytical doping profile having lateral st...Show More

Lateral Straggle Based Interface Trap Sensitivity in n-p-n SOI Double Gate TFETs

Deepjyoti Deb;Saurav Nath;Prachuryya Subash Das;Ratul Kr Baruah;Rupam Goswami

Year: 2024 | Conference Paper |

Random Telegraph Noise Due to Dielectric-Semiconductor Interface Traps in MOS Transistors

Deepjyoti Deb;Rupam. Goswami;Ratul. Kr. Baruah

IEEE Transactions on Dielectrics and Electrical Insulation
Year: 2024 | Early Access Article |
Random telegraph noise (RTN), primarily an gate dielectric-semiconductor interfacial phenomenon in field-effect transistors, is an important parameter of interest for downscaled devices. Existing methods proposed so far do not predict RTN, and are fundamentally focused on tracing RTN signals from raw experimental data. Commonly used modern technology computer-aided design (TCAD) tools are equipped...Show More

Random Telegraph Noise Due to Dielectric-Semiconductor Interface Traps in MOS Transistors

Deepjyoti Deb;Rupam. Goswami;Ratul. Kr. Baruah

Year: 2024 | Early Access Article |

Spiderweb-Based Interconnects for Smart Textile Applications

Ananya Bhattacharjee;Ratul K. Baruah

IEEE Journal on Flexible Electronics
Year: 2024 | Volume: 3, Issue: 6 | Journal Article |
Spiderwebs, or orbwebs, are naturally occurring structures that exhibit remarkable mechanical resilience and optimization. They are capable of withstanding multidirectional forces, even if one or more spiral or even radial lines are detached. Spiderweb (or fractal web) design holds significant interest in various fields such as flexible circuits, displays, smart textiles, and wearable healthcare. ...Show More

Spiderweb-Based Interconnects for Smart Textile Applications

Ananya Bhattacharjee;Ratul K. Baruah

Year: 2024 | Volume: 3, Issue: 6 | Journal Article |

Honeycomb-Inspired Interconnects for Large-Area Flexible Circuits: Simulation and Modeling

Ananya Bhattacharjee;Ratul K. Baruah

IEEE Transactions on Electron Devices
Year: 2024 | Volume: 71, Issue: 5 | Journal Article |
Cutting-edge interconnect design is crucial for flex circuits to achieve optimal signal integrity and transmit signals efficiently among various devices, even under mechanical and electrical strain. In this study, we inspected the suitability of using honeycomb-inspired stretchable connectors in flex circuits, stretched in two orientations: zigzag and armchair under mechanical and electrical stres...Show More

Honeycomb-Inspired Interconnects for Large-Area Flexible Circuits: Simulation and Modeling

Ananya Bhattacharjee;Ratul K. Baruah

Year: 2024 | Volume: 71, Issue: 5 | Journal Article |

Design of 3 bit/cell NAND Memory Array Based on Ferroelectric Field Effect Transistor

Albert Daimari;Ankit Chakusaru Deori;Amab Ratna Pawe;Ratul Kumar Baruah

2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)
Year: 2024 | Conference Paper |
Ferroelectric Field Effect Transistor (FeFET) based on HfO2 material has been actively studied in the recent times because of its small size, non-volatile memory retention and CMOS fabrication compatibility and as an alternative to NAND flash. So far only single/dual-level cell NAND array based on FeFET are reported. In this work a triple level cell (3 bit/cell) FeFET-based NAND Memory array is de...Show More

Design of 3 bit/cell NAND Memory Array Based on Ferroelectric Field Effect Transistor

Albert Daimari;Ankit Chakusaru Deori;Amab Ratna Pawe;Ratul Kumar Baruah

Year: 2024 | Conference Paper |

Possibility of Using Fractal Web Based Interconnects in Smart Textiles in Terms of Mechanical and Electrical Performance

Ananya Bhattacharjee;Ratul Kumar Baruah

2023 IEEE International Flexible Electronics Technology Conference (IFETC)
Year: 2023 | Conference Paper |
Cited by: Papers (1)
Spiderweb is a naturally available mechanically robust and optimized structure, which can withstand multidirectional forces even one or more spiral or even radial lines are cut. Recently, the spiderweb (fractal web) design has received significant interest in flex circuits, displays, smart textiles, wearable healthcare etc. In this work, a three order spiderweb hexagonal interconnect architecture ...Show More

Possibility of Using Fractal Web Based Interconnects in Smart Textiles in Terms of Mechanical and Electrical Performance

Ananya Bhattacharjee;Ratul Kumar Baruah

Year: 2023 | Conference Paper |

Mechanical and Electrical Performance of Stretchable Honeycomb Interconnect with Aspect Ratio Variation

Ananya Bhattacharjee;Ratul Kumar Baruah

2023 IEEE Devices for Integrated Circuit (DevIC)
Year: 2023 | Conference Paper |
Cited by: Papers (3)
Structural design engineering of interconnects in flexible electronics is an interesting study to understand the signal integrity and transmission of a signal between multiple devices over a circuit layer under different types of mechanical stress. The geometric design of flexible interconnects makes an important role in understanding the device functionality and optimization over a layout area. I...Show More

Mechanical and Electrical Performance of Stretchable Honeycomb Interconnect with Aspect Ratio Variation

Ananya Bhattacharjee;Ratul Kumar Baruah

Year: 2023 | Conference Paper |

Modelling of Surface Potential and Threshold Voltage for Short Channel Junctionless Cylindrical Gate-All-Around MOSFET

Supriya Khatoniar;Sujay Routh;Dhiman Malakar;Ratul Kumar Baruah

2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)
Year: 2022 | Conference Paper |
This work aims for an analytical model of surface potential and threshold voltage for a short channel Junctionless Cylindrical Gate All-Around (JL-CGAA) transistor. Surface potential has been derived from 2-D Poisson’s equation for cylindrical structure with some effective approximations and suitable boundary conditions considering both fixed charges and mobile charges of the device, using Evanesc...Show More

Modelling of Surface Potential and Threshold Voltage for Short Channel Junctionless Cylindrical Gate-All-Around MOSFET

Supriya Khatoniar;Sujay Routh;Dhiman Malakar;Ratul Kumar Baruah

Year: 2022 | Conference Paper |

Electrical Performance of Fractal Web as Flexible Interconnects

Ananya Bhattacharjee;Ratul Kumar Baruah

2022 IEEE Latin American Electron Devices Conference (LAEDC)
Year: 2022 | Conference Paper |
Cited by: Papers (2)
Spiderweb is one of the most mechanically robust and optimized naturally available structure, which can withstand multidirectional forces, in addition to the fact that the structure works even if one or more spiral lines are broken. Such a design can be worked with as an important model to develop conformal, lightweight, and stretchable electronic configuration like arrays of sensors environment f...Show More

Electrical Performance of Fractal Web as Flexible Interconnects

Ananya Bhattacharjee;Ratul Kumar Baruah

Year: 2022 | Conference Paper |

Junctionless Tunnel FET for High-Temperature Applications from an Analog Design Perspective

Sujay Routh;Deepjyoti Deb;Ratul K Baruah;Rupam Goswami

2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO)
Year: 2022 | Conference Paper |
Cited by: Papers (4)
Junctionless transistor (JLT) is known for improved short channel effects (SCE) and hence better scalability, and high temperature advantages, in addition that it offers more convenient fabrication steps. A Tunnel Field Effect Transistor (TFET) offers theoretically possible limit of subthreshold swing (SS) and has applicability for low power electronics. TFETs demonstrated in junctionless mode led...Show More

Junctionless Tunnel FET for High-Temperature Applications from an Analog Design Perspective

Sujay Routh;Deepjyoti Deb;Ratul K Baruah;Rupam Goswami

Year: 2022 | Conference Paper |

An SOI n-p-n Double Gate TFET for Low Power Applications

Deepjyoti Deb;Rupam Goswami;Ratul Kr Baruah;Kavindra Kandpal;Rajesh Saha

2021 Devices for Integrated Circuit (DevIC)
Year: 2021 | Conference Paper |
Cited by: Papers (6)
This article proposes a tunnel field effect transistor (TFET) based on n-p-n silicon body with double gates, one each over the two p-n junctions. The p-type source region is elevated as compared to the two n-type drain regions in order to create sufficient length for gate placement, and cover the junction. Electrical parameters have been systematically investigated through calibrated TCAD (technol...Show More

An SOI n-p-n Double Gate TFET for Low Power Applications

Deepjyoti Deb;Rupam Goswami;Ratul Kr Baruah;Kavindra Kandpal;Rajesh Saha

Year: 2021 | Conference Paper |

A low power intelligent helmet system

Albert Daimary;Meghna Goswami;Ratul Kumar Baruah

2018 International Symposium on Devices, Circuits and Systems (ISDCS)
Year: 2018 | Conference Paper |
Cited by: Papers (5)
A low power intelligent helmet system is reported in this paper which ensures the safety of a two-wheeler rider. The primary concept behind the working of the system is that the ignition of a two-wheeler will be enabled only if the rider is wearing a helmet and not consuming alcohol. An alcohol sensor and helmet wearing sensitive switches are installed inside a helmet, which is connected wirelessl...Show More

A low power intelligent helmet system

Albert Daimary;Meghna Goswami;Ratul Kumar Baruah

Year: 2018 | Conference Paper |

Impact of active well biasing on process-induced variations of a bulk planer junctionless transistor

Ratul Kumar Baruah;Roy P. Paily

2016 3rd International Conference on Emerging Electronics (ICEE)
Year: 2016 | Conference Paper |
Cited by: Papers (1)
In this paper, the impact of process parameters namely gate length (L), thickness of silicon film (Tsi) and gate oxide thickness (Tox) with increased well bias on the electrical parameters viz., drain current (ID), threshold voltage (VT), subthreshold slope (SS) and drain induced barrier lowering (DIBL) of a short-channel bulk planer junctionless transistor (BPJLT) are systematically investigated ...Show More

Impact of active well biasing on process-induced variations of a bulk planer junctionless transistor

Ratul Kumar Baruah;Roy P. Paily

Year: 2016 | Conference Paper |

Impact of fringing fields in a p-channel junctionless transistor

Ratul Kumar Baruah;Roy P. Paily

2014 IEEE 2nd International Conference on Emerging Electronics (ICEE)
Year: 2014 | Conference Paper |
Cited by: Papers (2)
This paper investigates the effects of fringing field arising out of high-k (dielectric constant) gate insulator on the device performance of a p-channel double-gate junctionless transistor (p-DGJLT). The overall device performance of a p-DGJLT is degraded with such fringing field. This behavior is similar to its n-channel counterpart of similar dimension. The effects of spacers on both sides of h...Show More

Impact of fringing fields in a p-channel junctionless transistor

Ratul Kumar Baruah;Roy P. Paily

Year: 2014 | Conference Paper |

A Dual-Material Gate Junctionless Transistor With High- $k$ Spacer for Enhanced Analog Performance

Ratul K. Baruah;Roy P. Paily

IEEE Transactions on Electron Devices
Year: 2014 | Volume: 61, Issue: 1 | Journal Article |
Cited by: Papers (123)
In this paper, we present a simulation study of analog circuit performance parameters for a symmetric double-gate junctionless transistor (DGJLT) using dual-material gate along with high- k spacer dielectric (DMG-SP) on both sides of the gate oxides of the device. The characteristics are demonstrated and compared with DMG DGJLT and single-material (conventional) gate (SMG) DGJLT. The DMG DGJLT pre...Show More

A Dual-Material Gate Junctionless Transistor With High- $k$ Spacer for Enhanced Analog Performance

Ratul K. Baruah;Roy P. Paily

Year: 2014 | Volume: 61, Issue: 1 | Journal Article |

Double-gate junctionless transistor for low power digital applications

Ratul Kumar Baruah;Roy P. Paily

2013 1st International Conference on Emerging Trends and Applications in Computer Science
Year: 2013 | Conference Paper |
Cited by: Papers (7)
In this paper, the performance of a short channel symmetric double-gate junctionless transistor (DGJLT) is reported at lower drain voltage aiming low power digital applications. The performance parameters namely drain current (ID), threshold voltage (VT), subthreshold slope (SS), drain induced barrier lowering (DIBL), and ON-state to OFFstate current ratio (ION/IOFF) for an n-channel DGJLT are sys...Show More

Double-gate junctionless transistor for low power digital applications

Ratul Kumar Baruah;Roy P. Paily

Year: 2013 | Conference Paper |

High-temperature effects on device performance of a junctionless transistor

Ratul Kumar Baruah;Roy P. Paily

2012 International Conference on Emerging Electronics
Year: 2012 | Conference Paper |
Cited by: Papers (8)
This paper presents the effects of high-temperature on the major digital and analog performance parameters of a 20-nm channel length n-type symmetric double-gate junctionless transistor (DGJLT) with the help of extensive device simulations. The characteristics are compared with conventional inversion mode counterpart i.e., double-gate transistor (DGMOS) of same dimension. It is found that the ON-s...Show More

High-temperature effects on device performance of a junctionless transistor

Ratul Kumar Baruah;Roy P. Paily

Year: 2012 | Conference Paper |

Estimation of process-induced variations in double-gate junctionless transistor

Ratul Kumar Baruah;Roy P. Paily

2012 5th International Conference on Computers and Devices for Communication (CODEC)
Year: 2012 | Conference Paper |
Cited by: Papers (7)
In this paper, the impact of process induced variations on the electrical characteristics of a junctionless symmetric double-gate transistor (DGJLT) is reported for the first time. The process parameters considered here are gate length (L), thickness of silicon film (Tsi) and gate oxide thickness (Tox). The impact of these process parameters on the electrical parameters viz., ON current, threshold...Show More

Estimation of process-induced variations in double-gate junctionless transistor

Ratul Kumar Baruah;Roy P. Paily

Year: 2012 | Conference Paper |

Analog performance of bulk planar junctionless transistor (BPJLT)

Ratul Kumar Baruah;Roy P. Paily

2012 Third International Conference on Computing, Communication and Networking Technologies (ICCCNT'12)
Year: 2012 | Conference Paper |
Cited by: Papers (9)
In this paper, analog performance of bulk planer junctionless transistor (BPJLT) is reported for the first time. The analog performance parameters, namely transconductance/drain current ratio (Gm/ID), intrinsic gain (GmRO) and unity gain frequency (fT) for n-type BPJLT are systematically investigated with the help of extensive device simulations. The results are then compared with silicon on insul...Show More

Analog performance of bulk planar junctionless transistor (BPJLT)

Ratul Kumar Baruah;Roy P. Paily

Year: 2012 | Conference Paper |

Silicon vs. germanium junctionless double-gate field effect transistor

Ratul Kumar Baruah

2012 International Conference on Devices, Circuits and Systems (ICDCS)
Year: 2012 | Conference Paper |
Cited by: Papers (2)
In this paper, performance of 20-nm germanium symmetric double-gate junctionless transistor (DGJLT) is evaluated and compared with silicon DGJLT. The performance parameters, namely drain current (Id), threshold voltage (Vt) drain induceed barrier lowering (DIBL), subthreshold slope (SS), transconductance/drain current ratio (Gm/Id) and drain output conductance (GD) are systematically investigated ...Show More

Silicon vs. germanium junctionless double-gate field effect transistor

Ratul Kumar Baruah

Year: 2012 | Conference Paper |

An Analytic Solution of Channel Potential and Drain Current for an Undoped Symmetric DG MOSFET Using SiO2 and High K Gate Dielectrics

Ratul Kr. Baruah;Sunando Das;Pallabjyoti Saikia;Himangshu Deka

2011 International Conference on Nanoscience, Technology and Societal Implications
Year: 2011 | Conference Paper |
In this work, we have presented a new analytical potential and current model for an undoped symmetric double- gate (DG) MOSFET which is valid from low to high drain-source voltages. The models are derived from an analytical solution of 2-D Poisson's equation. From the analytic solutions, explicit expressions for potential, electric field, mobile charge density and current have been derived. Simula...Show More

An Analytic Solution of Channel Potential and Drain Current for an Undoped Symmetric DG MOSFET Using SiO2 and High K Gate Dielectrics

Ratul Kr. Baruah;Sunando Das;Pallabjyoti Saikia;Himangshu Deka

Year: 2011 | Conference Paper |

Quantum Mechanical Treatment on Modeling of Drain Current, Capacitances and Transconductances for Thin Film Undoped Symmetric DG MOSFETs

Nipanka Bora;Ratul Kr. Baruah

2011 International Conference on Nanoscience, Technology and Societal Implications
Year: 2011 | Conference Paper |
Cited by: Papers (6)
In this work we present a semi-analytical model for the current voltage and Capacitance-Voltage characteristics of nano scaled undoped symmetric double gate (DG) MOSFETs. This model uses a parabolic potential approximation for the body potential whose coordinate is normal or perpendicular to the interfaces in all regions of device operation. The carrier confinement phenomenon is considered and we ...Show More

Quantum Mechanical Treatment on Modeling of Drain Current, Capacitances and Transconductances for Thin Film Undoped Symmetric DG MOSFETs

Nipanka Bora;Ratul Kr. Baruah

Year: 2011 | Conference Paper |

Concept of "Crossover Point" and its Application on Threshold Voltage Definition for Undoped-Body Transistors

Ratul Kumar Baruah;Santanu Mahapatra

2009 22nd International Conference on VLSI Design
Year: 2009 | Conference Paper |
Cited by: Papers (2)
As the conventional MOSFET's scaling is approaching the limit imposed by short channel effects, Double Gate (DG) MOS transistors are appearing as the most feasible candidate in terms of technology in sub-45 nm technology nodes. As the short channel effect in DG transistor is controlled by the device geometry, undoped or lightly doped body is used to sustain the channel. There exits a disparity in ...Show More

Concept of "Crossover Point" and its Application on Threshold Voltage Definition for Undoped-Body Transistors

Ratul Kumar Baruah;Santanu Mahapatra

Year: 2009 | Conference Paper |

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