High-temperature effects on device performance of a junctionless transistor

This paper presents the effects of high-temperature on the major digital and analog performance parameters of a 20-nm channel length n-type symmetric double-gate junctionless transistor (DGJLT) with the help of extensive device simulations. The characteristics are compared with conventional inversion mode counterpart i.e., double-gate transistor (DGMOS) of same dimension. It is found that the ON-state current increases very marginally with increase in temperature for DGJLT unlike DGMOS in which it decreases. The drain current with respect to drain voltage increases negligibly with increase in temperature for DGJLT, whereas it decreases for DGMOS. Intrinsic gain is almost independent of temperature at higher gate voltage (> 0.6 V) for DGJLT.

I. Introduction

As the channel length (L) of conventional metal-oxide semiconductor field - effect transistors (MOSFETs) is approaching ~10 nm, these devices face technological challenges due to very steep doping profile requirement at the pn junctions and high thermal budget. To resolve the issue, device architectures without junctions in source-channel-drain path have recently been explored. A junctionless transistor (JLT) has homogeneous and uniform doping throughout the source-channel-drain regions. JLTs have many advantages over conventional MOSFETs such as better SCE performance (reduced drain induced barrier lowering (DIBL) and subthreshold slope (SS) degradation) resulting better scalability, less sensitive to doping fluctuations and negative bias thermal instability, greatly simplified process flow and low thermal budgets after gate formation [1]–[4].