An SOI n-p-n Double Gate TFET for Low Power Applications

This article proposes a tunnel field effect transistor (TFET) based on n-p-n silicon body with double gates, one each over the two p-n junctions. The p-type source region is elevated as compared to the two n-type drain regions in order to create sufficient length for gate placement, and cover the junction. Electrical parameters have been systematically investigated through calibrated TCAD (technology computer aided design) simulations with objectives to reduce the ambipolar currents, and increase the ratio of on and off currents. Gate-on-drain length is an important parameter to control ambipolarity in the device, similar to gate-drain underlap length in conventional TFETs. Sub-60 mV/dec subthreshold swings, and drain current usually in order of tens of μA/μm have been observed. Gate workfunction engineering further shows the tuning of threshold voltage, and other electrical parameters.

I. Introduction

The lookout for alternatives to metal oxide field effect transistors (MOSFETs) for low power applications has been met with a number of novel devices in the past two decades [1]-[3]. Of such emerging devices which possess the promises to counter effects of downscaling, tunnel field effect transistors (TFETs) have acquired great attention due to their ability to offer sub-kT/q subthreshold swing (SS) and low leakage current [4]-[6]. The phenomenon of quantum tunneling in TFETs as opposed to thermionic emission in MOSFETs attributes negligible short channel effects to the former. Most commonly a gated reverse-biased p-i-n structure, TFETs come with drawbacks of low on-state current (I_ON), and acute ambipolarity. There have been many architectures, and techniques proposed so far to tackle these drawbacks. Of them, the double gate TFETs [7], gate-drain underlap TFETs [8], p-n-p-n TFETs [9], halo-pocket TFETs [10], heterojunction TFETs [11], and hetero-gate TFETs [12] are some of the prominent ones.