Estimation of process-induced variations in double-gate junctionless transistor

In this paper, the impact of process induced variations on the electrical characteristics of a junctionless symmetric double-gate transistor (DGJLT) is reported for the first time. The process parameters considered here are gate length (L), thickness of silicon film (Tsi) and gate oxide thickness (Tox). The impact of these process parameters on the electrical parameters viz., ON current, threshold voltage (V_T) and subthreshold slope (SS) are systematically investigated with the help of extensive device simulations and compared with conventional symmetric doublegate transistor (DGMOS). It is seen that ON current variation with silicon thickness is higher for DGJLT compared to DGMOS. Threshold voltage of DGJLT is more sensitive to silicon thickness and gate oxide thickness as compared to DGMOS. The overall SS variation is negligible in DGJLT compared to DGMOS.

I Introduction

Multigate silicon on insulator metal-oxide semiconductor field-effect transistors (SOI MOSFETs) are being studied by semiconductor industries as a response to several effects resulting from shrinking of gate length (L) in planar MOSFETs to ultra low value (L=10 nm or less), due to its scaling capability and technology compatibility. However, the ultra sharp source and drain junctions impose challenges in doping profile and thermal budget making the fabrication process very complex. Junctionless transistor (JLT), which does not have pn junctions in the source-channel-drain path, resolves the issue. A JLT has uniform doping throughout the source-channel-drain regions.