Contents I. Introduction
The device dimensions of metal-oxide-semiconductor field effect transistors (MOSFET) have been reduced continuously over the past few decades to achieve improved microprocessor speed and memory storage capacity. As the channel length reduces to sub-20 nm regime, the conventional MOSFET is approaching the limits, imposed by severe short channel effects (SCEs) and steep doping profile requirement at source and drain junctions. To get rid of SCEs, several techniques like channel engineering, high-k gate dielectrics etc. have been incorporated in bulk single/multigate transistors. Multigate silicon-on-insulator (SOI) transistor came as a replacement of conventional bulk transistors in such short channel regime. These devices are reported to have much lowered SCEs than the bulk MOSFETs. Thus, SOI transistors can be scaled to lower channel length. But, with ever increasing demand of higher device performance, the shrinking of these devices also face critical technological challenges and high thermal budget in sub 20-nm regime. As an alternate solution, device architectures without junctions in source-channel-drain path have recently been explored [1]–[2]. Named as “junctionless transistor (JLT)”, these devices are basically accumulation mode devices. JLTs have many advantages over conventional inversion mode MOSFETs such as better SCEs performance (reduced SS and DIBL), greatly simplified process flow and low thermal budgets after gate formation resulting in flexibility in the choice of materials for gate dielectric and gate metal etc [2]–[5]. However, a JLT offers lower drain current than IM devices.
