Contents I. Introduction
The concept of junctionless field-effect-transistor (JLT), implemented in single-gate/double-gate/triple-gate/gate-all-around architecture has recently been reported [1]–[9]. Another JLT topology reported is vertical slit FET [10]–[11]. The major differences of JLT with conventional inversion mode (1M) metal-oxide-semiconductor (MOS) transistor are that in a JLT, there is no pn junction along the source-channel-drain path, the channel is homogeneous, and has uniform doping and only majority carriers carry the current unlike in an inverted channel. In principle, a JLT is an accumulation mode (AM) kind of device except that in a typical AM transistor, the regions of operation are depletion and accumulation; however in JLT it is depletion, partial depletion and accumulation, i.e., in a JLT accumulation happens at a higher threshold voltage than in an AM device. In addition to lesser SCEs and simpler process flow [3], the junctionless technology offers lesser process variability (an exception to this trend is that the threshold voltage is more sensitive to random dopant fluctuations [6] and nanowire width variation [8] than its inversion mode counterpart), surface roughness scattering [10], random telegraph-noise [4] and flicker noise [5] etc. Though bulk mobility of electron is low at higher channel doping , it increases with applied gate voltage. This is because of the screening of ionized impurities by the accumulation electrons and as a result, coulomb scattering is reduced, which increases mobility [3]. Hence, the drain current of JLT is appreciable and comparable to that in inversion mode devices though its value may not exceed the latter. JLT has lesser OFF-state current and hence it is more scalable to lower channel lengths than 1M devices are. Output current and transconductance of JLT are inferior to an 1M device, which is the major drawback of JLT.
