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Low IF CMOS Receiver with 3-Stage LNA for Sub-GHz Communication
Shivam Kumar Jha;Apsana Khatoon;Priyanka Tiwari;Dipti;Kavindra Kandpal;Manish Goswami;Prasanna Kumar Misra
2024 IEEE International Symposium on Smart Electronic Systems (iSES)
Year: 2024 | Conference Paper |
In this paper, the low-IF architecture for CMOS receiver is explored for narrow-band, long-range applications for the frequency band of 865–867 MHz. The challenges in the receiver design and integration issues of low noise amplifier, mixer, filter, variable gain amplifier, sample and hold circuit, 4 - bit analog to digital converter are discussed. The performance of receiver is optimized using UMC...Show More
Highly Reliable, Feed-Forward and Multi-Arbiter based Physical Unclonable Function for IoT security
Nitish Kumar;Sneha Chaudhary;Kavindra Kandpal;Manish Goswami
2024 IEEE International Symposium on Smart Electronic Systems (iSES)
Year: 2024 | Conference Paper |
As the Internet of Things (IoT) evolves, securing IoT-enabled devices has become crucial due to the risk of increased cyber-attacks. The cryptographic methods used traditionally are unsuitable for IoT nodes due to their limited resources. Physically Unclonable Functions offer a cost-effective solution by generating unique keys from the inherent random variations in integrated circuits through chal...Show More
Split Topology Based 8-Bit Flash ADC Architecture for Reduced Conversion Time
Anurag Pandey;Dipti;Ajinkya Kulkarni;Kavindra Kandpal;Prasanna Kumar Misra;Manish Goswami
2024 IEEE Region 10 Symposium (TENSYMP)
Year: 2024 | Conference Paper |
This paper presents the design of 8-bit flash ADC architecture using split based technique. The proposed design requires only 2(2^{N/ 2}-1) number of comparators for N-bit of resolution and occupies only 30 comparators for 8-bit flash ADC instead of 255 comparators. The proposed architecture has resulted in less number of comparators due to split topology and incorporating intermediate stage in ...Show More
A 5T-2C Current-Biased Voltage-Programmed (CBVP) Pixel circuit for AMOLED Displays
2023 IEEE Workshop on Recent Advances in Photonics (WRAP)
Year: 2023 | Conference Paper |
In this work, a 5T2C current-biased voltage-programmed (CBVP) pixel circuit is put forth as the backplane technology for AMOLED displays. The designed pixel circuit uses a very low input bias current $(\mathrm{I}_{\text{BIAS}})$ of 0.1 $\mu \mathrm{A}$ compared to existing designs. It also compensates for the OLED current (IOLED) error for a maximum 1.35 V threshold voltage shift. The maximum emis...Show More
Multiplexer & Memory Efficient Bit-Reversal Algorithms
Basamgari Bhanu Prakash Reddy;Nitish Kumar;Kavindra Kandpal;Manish Goswami
2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Year: 2023 | Conference Paper |
This paper presents novel approaches for obtaining bit reversal. Bit reversal plays a prominent role in Fast Fourier Transform (FFT) algorithm. It is used to sort out the FFT algorithm's output, which often is in a bit-reversed order [1]. The proposed circuits consist of memories, multiplexers, counters and a bit-reversal circuit. This paper also proposes several single & dual memory-based bit-rev...Show More
Design and Analysis of Low-Voltage, MOS-only Bandgap Reference Circuit
Tej Prakash Sahu;Ritesh Kumar Tiwari;Prasanna Kumar Misra;Manish Goswami;Kavindra Kandpal
2023 IEEE International Symposium on Smart Electronic Systems (iSES)
Year: 2023 | Conference Paper |
This paper presents a novel MOS-only voltage reference with a very low-temperature coefficient (TC) and is immune to power supply variation. It uses a power supply of 1.2 V and can even operate on a voltage of more than 800 mV. The circuit is simulated using PTM 65 nm models on Cadence. Proportional to absolute (PTAT) current is generated by biasing MOS in the subthreshold region and generating th...Show More
Design and Optimization of a Gilbert Cell Down-Conversion Mixer for Improved Linearity, Noise Figure, and Conversion Gain
Dornala Santhoshi;Brij Kumar Bharti;Amarnath Yadav;Kavindra Kandpal
2023 10th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)
Year: 2023 | Conference Paper |
Cited by: Papers (1)
This paper discusses a design process for a balancing Noise Figure, Conversion Gain, Linearity, and Power Consumption for Gilbert cell mixer topology based on 90 nm CMOS technology utilizing the Voltage Biasing technique. The simulation run on the optimized model shows a conversion gain of 10.034 dB, an input third-order intercept point at 9.68 dBm, a noise figure of 9.51 dB, and a power consumpti...Show More
Design of a Low-Voltage and Reduced Programming cycle AMOLED Pixel Circuit using IGZO TFTs
2022 IEEE International Conference on Emerging Electronics (ICEE)
Year: 2022 | Conference Paper |
Cited by: Papers (1)
This work presents a 5T −2C pixel circuit based on amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) for flexible displays utilizing improved stacked voltage-programmed pixel circuit topology. Due to a low operating voltage of 5 V and reduced programming time of 8 $\mu\mathrm{s}$, the proposed circuit finds its application in large screen HD displays as it can provide a ver...Show More
FPGA Based Resource Efficient Simulation and Emulation Of Grover’s Search Algorithm
2022 IEEE 19th India Council International Conference (INDICON)
Year: 2022 | Conference Paper |
The introduction of quantum computing has led to an immense increase in performance of various search and encryption algorithms. However the practical realization of quantum computers is1 a challenging task. Hence quantum algorithms are being modeled on classical platforms. Hardware emulation of quantum computers has been found to be more effective than software simulations. In this paper, Grover'...Show More
Design of 7T-2C a-IGZO based pixel circuit for flexible AMOLED displays
2022 IEEE 19th India Council International Conference (INDICON)
Year: 2022 | Conference Paper |
Cited by: Papers (1)
This work proposes an AC biased pixel circuit employing flexible amorphous-Indium Gallium Zinc Oxide (a- IGZO) thin film transistors (TFT) to compensate for threshold voltage, mobility, and OLED deterioration for AMOLED displays. In the circuit, there are seven TFTs and two capacitors and is voltage programmed. The designed circuit was simulated using the HSpice tool and an adapted level 61 model ...Show More
Effect of deep and tail grain boundary trap states on the performance of poly-ZnO TFT
Saurabh Jaiswal;Sairam Akula;Rupam Gosawmi;Manish Goswami;Kavindra Kandpal
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)
Year: 2022 | Conference Paper |
Cited by: Papers (1)
The presence of grain boundaries in polycrystalline ZnO hugely impacts its electrical characteristic. In this work, we have studied the influence of double exponential grain boundary (GB) traps on the performance of a ZnO TFT. It is assumed that all kinds of defects in the ZnO/ gate-dielectric interface and GB are effectively localized in GB traps. Moreover, traps are thermally activated as per th...Show More
Impact of Gaussian Grain Boundary Trap States on the Performance of the LTPS TFTs
Saurabh Jaiswal;Manoj Kumar Singh;Rupam Gosawmi;Manish Goswami;Kavindra Kandpal
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)
Year: 2022 | Conference Paper |
Cited by: Papers (1)
This paper presents a study on the impact of grain boundary trap states on the performance of polysilicon thin-film transistors (TFTs. It uses the Synopsys TCAD tool to analyze the device behavior of low-temperature polysilicon (LTPS) TFTs. It has been observed that grain boundary traps in polycrystalline material adversely impact the threshold voltage, subthreshold slope, and mobility. Across the...Show More
Concurrent Dual Band CMOS LNA with improved IIP3 using Modified DS technique
2022 IEEE International Symposium on Smart Electronic Systems (iSES)
Year: 2022 | Conference Paper |
Cited by: Papers (2)
For concurrent Dual-band low noise amplifiers (DB-LNA), this work provides a technique of linearization which enhances input third-order intercept point (IIP3) along with an improved output matching network, designed using a 65 nm CMOS technology for wireless and Bluetooth applications. For the linearization of dual-band LNAs, modified derivative superposition (DS) technique is described which sug...Show More
A 14 nm Single-Ended Schmitt Trigger SRAM Cell for Improved SNM & Delay
2022 IEEE International Symposium on Smart Electronic Systems (iSES)
Year: 2022 | Conference Paper |
The recent advancements in Very Large Scale Integrated (VLSI) system design shows that the speed of memory contributes to the overall delay of the system which plays a vital role in terms of high-speed electronic systems. In this paper, a 9 Transistor Static Random Access Memory (9T-SRAM) cell has been proposed in 14nm Fin Field-Effect Transistor (FinFET) technology node incorporating a Low-Power ...Show More
Design of Hexagonal Oscillator for True Random Number Generation
Krishan Mehra;Dhirendra Kumar;Kavindra Kandpal;Prasanna Kumar Misra;Manish Goswami
2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Year: 2022 | Conference Paper |
Cited by: Papers (2)
This paper presents the design of a low power, high speed true random number generator (TRNG) based on hexagonal ring oscillator-based topology targeted for cryptographic application. The proposed design takes the advantage of jitter provided by the two hexagonal oscillators to produce highly random sequence. The hexagonal oscillator improves the level of entropy due to more number of oscillating ...Show More
A 0.18 pJ/Conversion Step Hybrid Structure based ADC
Dipti;Shipra Gaur;Kavindra Kandpal;Prasanna Kumar Misra;Manish Goswami
2022 2nd Asian Conference on Innovation in Technology (ASIANCON)
Year: 2022 | Conference Paper |
This paper presents the hybrid design of 8 bit ADC incorporating binary search ADC for area saving and flash ADC for higher speed operation. This ADC architecture is divided into two stages: the first stage is designed using binary search topology while the second stage is designed using flash architecture. The binary search stage is set to generate only 6 bits and flash stage is set to generate r...Show More
Performance of Topological Insulator (Sb2Te3)-Based Vertical Stacking Photodetector on n-Si Substrate
Sandeep Kumar Verma;Kavindra Kandpal;Pramod Kumar;Arun Kumar;Claudia Wiemer
In this work, we report the photodetector properties of a vertically stacked heterostructure based on topological insulator Sb2Te3/n-Si. The high-quality Sb2Te3 thin films were grown on an n-Si substrate by the metal–organic chemical vapor deposition (MOCVD) technique. The fabricated Sb2Te3/n-Si heterostructure devices promise to work as an excellent rectification diode with an excellent rectifica...Show More
A ZnO Humidity Sensor integrated with a-IGZO TFT based Preamplifier
2021 IEEE 18th India Council International Conference (INDICON)
Year: 2021 | Conference Paper |
Cited by: Papers (1)
In this work, a Zinc Oxide (ZnO) nanorods based humidity sensor integrated with an amorphous-Indium Gallium Zinc Oxide (a-IGZO) TFT-based preamplifier has been presented. The humidity sensor is modeled in a Wheatstone Bridge configuration with the ZnO nanorods grown onto one of its quadrants. Calibrated SPICE level-3 models are used for a-IGZO TFTs. The proposed TFT-based preamplifier uses a two-s...Show More
IoT Enabled Cost-Effective Integrated Industrial Automation For FMCG Industry
Kingsuk Bag;Shivam Vaishampayan;Shakti Majhwar;Manish Goswami;Kavindra Kandpal
2021 IEEE 8th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)
Year: 2021 | Conference Paper |
Cited by: Papers (1)
Each industry aims to improve efficiency and decrease production costs. Small manufacturers struggle to survive and prosper due to the competition from large Multinational Corporations (MNC’s). The main reason behind this is the lack of automation and the high cost of modern technologies. The aim is to design and implement an integrated and automated prototype of Industrial Automation for the Fast...Show More
A 6.22pJ/conv-step Split Design and Subtractor Based Binary Search ADC
2021 International Conference on Electrical, Computer, Communications and Mechatronics Engineering (ICECCME)
Year: 2021 | Conference Paper |
This paper presents the design of 8-bit asynchronous based binary search analog to digital converter (ADC) using split design topology. In the proposed work, the 8 bits had been realized using two stages of 4 bits each with a subtractor in between. The use of such asynchronous design had resulted in reduction of switching network, reduced number of comparator and improvement in speed and chip area...Show More
Design of Energy Efficient True Random Number Generator using MUX-Metastable Approach
Dhirendra Kumar;Himanshu Kesarwani;Kavindra Kandpal;Prasanna Kumar Misra;Manish Goswami
2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)
Year: 2021 | Conference Paper |
Cited by: Papers (3)
The design of a meta-stable ring oscillator-based true random number generator (TRNG) is presented in this paper. The proposed circuit is designed in 40nm CMOS technology and simulated in cadence virtuoso simulation environment using a combination of current starved-based ring oscillators (ROs), multiplexer, linear feedback shift register (LFSR), UP/DOWN counter followed by a meta-stable circuit. ...Show More
Smart Switching Network based Asynchronous Binary Search ADC
Dipti Dipti;Chetna Kaushik;Kavindra Kandpal;Prasanna Kumar Misra;Manish Goswami
2021 International Conference on Communication information and Computing Technology (ICCICT)
Year: 2021 | Conference Paper |
This paper presents a binary search analog to digital converter based on sub-ADC scheme in which the 16-bit architecture is split into four stages and the whole architecture uses only N comparators instead of (2N-1) comparators. The proposed design enables comparators in sequential manner using asynchronous logic and achieves low power and less chip area with high conversion speed. The proposed bi...Show More
An SOI n-p-n Double Gate TFET for Low Power Applications
Deepjyoti Deb;Rupam Goswami;Ratul Kr Baruah;Kavindra Kandpal;Rajesh Saha
This article proposes a tunnel field effect transistor (TFET) based on n-p-n silicon body with double gates, one each over the two p-n junctions. The p-type source region is elevated as compared to the two n-type drain regions in order to create sufficient length for gate placement, and cover the junction. Electrical parameters have been systematically investigated through calibrated TCAD (technol...Show More
A low power, charge-sensitive preamplifier integrated with a silicon nanowire biosensor
2021 IEEE Latin America Electron Devices Conference (LAEDC)
Year: 2021 | Conference Paper |
Cited by: Papers (2)
Charge amplifiers, characterized by their charge-sensitivity or charge gain, are essential components of a transducer-interfacing system that amplify charge signals emerging from various sensors and convert them into voltage signals. Today, with increased scaling of MOSFETs, it becomes challenging to obtain the charge amplifiers with high charge sensitivity and low power. Furthermore, if the charg...Show More
Device-To-Circuit Integrated Design of DMFET Biosensor and Its Readout Using CMOS Pre-charge Amplifier
2020 IEEE 17th India Council International Conference (INDICON)
Year: 2020 | Conference Paper |
Cited by: Papers (1)
Dielectric Modulated Field Effect Transistor (DMFETs) offer advantages over many other well-known biosensors, making them extremely important in the fields of medicines and diagnostics. The paper aims to model a DMFET using the SPICE Level-3 model. This adapted model of the DMFET sensor can be used to detect the presence of both the charged as well as uncharged biomolecules in the nanogap cavity e...Show More
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