Contents I. Introduction
The Conventional metal–oxide–semiconductor field-effect transistors (MOSFETs) impose challenges, such as enlarged gate leakage and added serious short-channel effects (SCEs) with the continuous miniaturization of device sizes at nanoscale regime. Multiple gate FETs have better scalability due to its superior controllability of the gates on the channel region. However, very abrupt source and drain junctions requirement put challenges in doping profile techniques and thermal budget. Junctionless transistor (JLT), which does not have p-n junction in the source–channel–drain path, has better SCEs performance resulting better scalability, greatly simplified process flow, low thermal budgets after gate formation, and so on [1]–[4]. However, JLTs suffer from lesser drain current and transconductance compared with inversion mode MOSFETs due to high doping concentration in the channel region [1], [5], [6].
