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R. Mulhaupt - IEEE Xplore Author Profile

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Author details

R. Mulhaupt

Publications

8

Citations

1,074

Publications by Year

20042007

Co-Authors:

M. AmbidF. CianiS. CliffordG. ColettiD. Fabiani

Show All Co-Authors (20)

R. Mulhaupt

Affiliation

Institute for Macromolecular Chemistry, University of Freiburg, Germany

Publication Topics

Space Charge,
Electrical Insulation,
Maleic Anhydride,
Silicate Minerals,
Charge Trapping,
Low Field,
Base Resin,
Conduction Mechanism,
Deep Trap,
Depolarization,
Electrode,
Insulation System

Biography

Rolf Mülhaupt was born on 13 September 1954 in Waldshut-Tiengen, Baden, Germany. In 1973–1978 he studied chemistry at the Albert-Ludwigs University in Freiburg. In 1978–1981 he studied for his Ph.D. degree at the Industrial and Engineering Chemistry Laboratory of the Swiss Federal Institute of Technology (ETH Zürich). In 1981–1985 he was a chemist at Du Pont Central Research in Wilmington, Delaware, USA and carried out research on catalytic olefin polymerization, functionalized polyolefins, engineering thermoplastics and gas separation membranes. In 1985–1989 he was a Group Leader at Ciba-Geigy AG, Plastics & Additives Research in Marly, CH, working on toughened epoxy resins, adhesion promoters and polyurethanes, U'V-curable adhesives, high...

Publications

8

Citations

1,074

Publications by Year

20042007

Co-Authors:

M. Ambid
F. Ciani
S. Clifford
G. Coletti
D. Fabiani

Show All Co-Authors (20)

Author's Published Works

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Showing 1-25 of 98 results

Conferences (74)

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Toshiba Corporation, Yokohama, Japan(10)
Microelectronics Engineering Laboratory, Toshiba Corporation, Kawasaki, Japan(9)
Toshiba Corporation, Kawasaki, Japan(9)
Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP(8)
Research and Development Center, Toshiba Corporation, Kawasaki, Japan(7)
IEEE Transactions on Electron Devices(21)
International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)(4)
1995 Symposium on VLSI Technology. Digest of Technical Papers(3)
1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)(3)
2023 35th International Conference on Microelectronic Test Structure (ICMTS)(3)
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Results

Model-Based Development to Improve Electrical and Thermal Performances for Robust Si Power MOSFETs Using Embedded Die Packaging Technology

Kentaro Mori;Kohei Oasa;Hitoshi Imi;Yutaro Hayashi;Tatsuya Ohguro;Tatsuya Nishiwaki;Fumiyoshi Kawashiro

2024 IEEE 10th Electronics System-Integration Technology Conference (ESTC)

Year: 2024 | Conference Paper |

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In this study, embedded die packaging technology was used to evaluate device characteristics and package-level reliability tests of 40V-rated Si MOSFETs for automotive applications. Initially, electrical and thermal simulations were performed to optimize the package design, followed by fabrication of a prototype package under optimal conditions. These results showed that increasing the number of l...Show More

Model-Based Development to Improve Electrical and Thermal Performances for Robust Si Power MOSFETs Using Embedded Die Packaging Technology

Kentaro Mori;Kohei Oasa;Hitoshi Imi;Yutaro Hayashi;Tatsuya Ohguro;Tatsuya Nishiwaki;Fumiyoshi Kawashiro

2024 IEEE 10th Electronics System-Integration Technology Conference (ESTC)

Year: 2024 | Conference Paper |

New Extraction Method for Intrinsic Qrr of Power MOSFETs

T. Hara;S. Nakajima;T. Ohguro;K. Miyashita

2023 35th International Conference on Microelectronic Test Structure (ICMTS)

Year: 2023 | Conference Paper |

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We provide the method to estimate intrinsic Qrr (

$Q_{r_{-}\text{int}})$ without parasitic inductance in the measurement system for the first time. In this paper, we analyze parasitic inductance dependence of Qrr by TCAD simulation and we propose the method for removing the parasitic inductance effect as well as calculating the carrier of recombination and discharge (qr_into).Show More

New Extraction Method for Intrinsic Qrr of Power MOSFETs

T. Hara;S. Nakajima;T. Ohguro;K. Miyashita

2023 35th International Conference on Microelectronic Test Structure (ICMTS)

Year: 2023 | Conference Paper |

On-Resistance Measurements of Low Voltage MOSFET at wafer level

Kohei Oasa;Tatsuya Nishiwaki;Tatsuya Ohguro;Yasunobu Saito;Yusuke Kawaguchi

2023 35th International Conference on Microelectronic Test Structure (ICMTS)

Year: 2023 | Conference Paper |

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To accelerate the development of low voltage MOSFET, we designed a test element group pattern that enables on-resistance measurement at wafer level. We confirmed that the on-resistance can be measured at wafer level by optimizing the device size and contact method to eliminate the influence of parasitic resistance.Show More

On-Resistance Measurements of Low Voltage MOSFET at wafer level

Kohei Oasa;Tatsuya Nishiwaki;Tatsuya Ohguro;Yasunobu Saito;Yusuke Kawaguchi

2023 35th International Conference on Microelectronic Test Structure (ICMTS)

Year: 2023 | Conference Paper |

Measuring of parasitic resistance of stacked chip of Si power device

Tatsuya Ohguro;Hideharu Kojima;Takuma Hara;Tatsuya Nishiwaki;Kenya Kobayashi

2023 35th International Conference on Microelectronic Test Structure (ICMTS)

Year: 2023 | Conference Paper |

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Stacked chip of! Si power device is useful for both lower on-resistance and small packaged size for reduction of system size and high power efficiency. In this paper, some structures and procedure to measure parasitic resistance of the stacked chip are described.Show More

Measuring of parasitic resistance of stacked chip of Si power device

Tatsuya Ohguro;Hideharu Kojima;Takuma Hara;Tatsuya Nishiwaki;Kenya Kobayashi

2023 35th International Conference on Microelectronic Test Structure (ICMTS)

Year: 2023 | Conference Paper |

Stacked chip of Si power device with double side Cu plating for low on-resistance

Tatsuya Ohguro;Hideharu Kojima;Takuma Hara;Tatsuya Nishiwaki;Shinichi Umekawa

2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Year: 2021 | Conference Paper |

Cited by: Papers (1)

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Stacked chip is the one of the candidate structure to realize low on-resistance, small package. In order to minimize the chip size, it is required to overlap two gate and two source electrodes between two stacked chips, respectively. However, it is impossible to overlap them when wire bonding are used. We completely overlapped these electrodes between two chips by Cu clips. Additionally, double si...Show More

Stacked chip of Si power device with double side Cu plating for low on-resistance

Tatsuya Ohguro;Hideharu Kojima;Takuma Hara;Tatsuya Nishiwaki;Shinichi Umekawa

2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Year: 2021 | Conference Paper |

Cu Double Side Plating Technology for High Performance and Reliable Si Power Devices

Hitoshi Kobayashi;Tatsuya Ohguro;Tetsuya Kai;Takako Motai;Masaaki Ogawa;Mie Matsuo;Kenichi Oohashi;Shinsuke Kozumi;Yoshiharu Takada;Hideharu Kojima;Shingo Masuko;Naoki Yonezawa;Akira Komatsu;Tatsuya Nishiwaki;Takuma Hara;Mari Takahashi;Akira Ezaki;Kenichi Ohtsuka;Seiji Inumiya;Kyoichi Suguro

2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Year: 2019 | Conference Paper |

Cited by: Papers (3)

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In this work, we have developed vertical Si power MOSFETs with high performance and high reliability by using Cu double side plating technology. 20 μ m thick Cu plating layers are formed on both sides of devices with 50 μ m thick Si substrate. In this structure, even though Si substrate is thinner, Safety Operating Area (SOA) is wider and the warpage of chip is smaller thanks to front and back sid...Show More

Cu Double Side Plating Technology for High Performance and Reliable Si Power Devices

Hitoshi Kobayashi;Tatsuya Ohguro;Tetsuya Kai;Takako Motai;Masaaki Ogawa;Mie Matsuo;Kenichi Oohashi;Shinsuke Kozumi;Yoshiharu Takada;Hideharu Kojima;Shingo Masuko;Naoki Yonezawa;Akira Komatsu;Tatsuya Nishiwaki;Takuma Hara;Mari Takahashi;Akira Ezaki;Kenichi Ohtsuka;Seiji Inumiya;Kyoichi Suguro

2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Year: 2019 | Conference Paper |

Alpha-Particle Shielding Effect of Thick Copper Plating Film on Power MOSFETs

Tatsuya Nishiwaki;Kohei Oasa;Kentaro Ichinoseki;Kikuo Aida;Tatsuya Ohguro;Yoshiharu Takada;Hideharu Kojima;Yusuke Kawaguchi

2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Year: 2019 | Conference Paper |

Cited by: Papers (4)

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We investigated characteristics impact of alpha-particles irradiation to power MOSFETs and demonstrated alpha-particle shielding effect of thick copper plating film on a power MOSFET. We used americium-241 alpha-source for irradiating alpha-particles to the surface of the power MOSFET die. Irradiation under gate-source bias caused threshold voltage (Vth) decrease due to generated trapped holes in ...Show More

Alpha-Particle Shielding Effect of Thick Copper Plating Film on Power MOSFETs

Tatsuya Nishiwaki;Kohei Oasa;Kentaro Ichinoseki;Kikuo Aida;Tatsuya Ohguro;Yoshiharu Takada;Hideharu Kojima;Yusuke Kawaguchi

2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Year: 2019 | Conference Paper |

Evaluation methodology for current collapse phenomenon of GaN HEMTs

Toru Sugiyama;Kohei Oasa;Yasunobu Saito;Akira Yoshioka;Takuo Kikuchi;Aya Shindome;Tatsuya Ohguro;Takeshi Hamamoto

2018 IEEE International Reliability Physics Symposium (IRPS)

Year: 2018 | Conference Paper |

Cited by: Papers (2)

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Methods of both evaluation and analysis of current collapse (C/C) in GaN HEMTs are discussed. Recently, guidelines to the methods of evaluation of C/C in comparing device characteristics have been required as the increase in on-resistance resulting from C/C depends significantly on stress conditions and the applied method. Therefore, as a guideline, we propose the DC voltage stress and inductance ...Show More

Evaluation methodology for current collapse phenomenon of GaN HEMTs

Toru Sugiyama;Kohei Oasa;Yasunobu Saito;Akira Yoshioka;Takuo Kikuchi;Aya Shindome;Tatsuya Ohguro;Takeshi Hamamoto

2018 IEEE International Reliability Physics Symposium (IRPS)

Year: 2018 | Conference Paper |

150 GHz FMAX with high drain breakdown voltage immunity by multi gate oxide dual work-function (MGO-DWF)-MO SFET

T. Miyata;H. Tanaka;K. Kagimoto;M. Kamiyashiki;M. Kamimura;A. Hidaka;M. Goto;K. Adachi;A. Hokazono;T. Ohguro;K. Nagaoka;Y. Watanabe;S. Hirooka;Y. Ito;S. Kawanaka;K. Ishimaru

2015 IEEE International Electron Devices Meeting (IEDM)

Year: 2015 | Conference Paper |

Cited by: Papers (4)

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We propose Multi Gate Oxide - Dual Work-Function (MGO-DWF)-MOSFET which is suitable for low power AB-class RF power amplifier (RF PA). This was examined for the first time by comparing with a standard Cascode connection circuitry composed of LV- and HVMOSFETs. Dramatically improved FMAX (150 GHz) with sufficient drain break-down voltage (VBD) was experimentally confirmed in a practical device stru...Show More

150 GHz FMAX with high drain breakdown voltage immunity by multi gate oxide dual work-function (MGO-DWF)-MO SFET

T. Miyata;H. Tanaka;K. Kagimoto;M. Kamiyashiki;M. Kamimura;A. Hidaka;M. Goto;K. Adachi;A. Hokazono;T. Ohguro;K. Nagaoka;Y. Watanabe;S. Hirooka;Y. Ito;S. Kawanaka;K. Ishimaru

2015 IEEE International Electron Devices Meeting (IEDM)

Year: 2015 | Conference Paper |

Unified Transient and Frequency Domain Noise Simulation for Random Telegraph Noise and Flicker Noise Using a Physics-Based Model

Yusuke Higashi;Nobuyuki Momo;Hiroki Sasaki;Hisayo Sasaki Momose;Tatsuya Ohguro;Yuichiro Mitani;Takamitsu Ishihara;Kazuya Matsuzawa

IEEE Transactions on Electron Devices

Year: 2014 | Volume: 61, Issue: 12 | Journal Article |

Cited by: Papers (15)

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Unified transient and frequency domain noise simulation of random telegraph noise and flicker noise is conducted using a multiphonon-assisted model that considers tunneling probabilities and energy transitions of discretized traps in the gate insulator of MOSFETs. The proposed model is able to concurrently represent the dynamic behavior of electron and hole trapping and detrapping via interactions...Show More

Unified Transient and Frequency Domain Noise Simulation for Random Telegraph Noise and Flicker Noise Using a Physics-Based Model

Yusuke Higashi;Nobuyuki Momo;Hiroki Sasaki;Hisayo Sasaki Momose;Tatsuya Ohguro;Yuichiro Mitani;Takamitsu Ishihara;Kazuya Matsuzawa

IEEE Transactions on Electron Devices

Year: 2014 | Volume: 61, Issue: 12 | Journal Article |

Scaling strategy for low power RF applications with multi gate oxide Dual Work function (DWF) MOSFETs utilizing self-aligned integration scheme

T. Miyata;S. Kawanaka;A. Hokazono;T. Ohguro;Y. Toyoshima

2013 Symposium on VLSI Technology

Year: 2013 | Conference Paper |

Cited by: Patents (1)

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Dual Work Function (DWF)-MOSFET of 100 nm gate length device with self-aligned integration scheme was demonstrated utilizing conventional CMOS platform process for the first time. Here, we obtained not only the improved transconductance (GM) and drain conductance (GD), but also the enlarged operation voltage window employing multi gate oxide structure combined with DWF gate stack. Also, the discri...Show More

Scaling strategy for low power RF applications with multi gate oxide Dual Work function (DWF) MOSFETs utilizing self-aligned integration scheme

T. Miyata;S. Kawanaka;A. Hokazono;T. Ohguro;Y. Toyoshima

2013 Symposium on VLSI Technology

Year: 2013 | Conference Paper |

The optimum device parameters for high RF and analog/MS performance in planar MOSFET and FinFET

T. Ohguro;Y. Higashi;K. Okano;S. Inaba;Y. Toyoshima

2012 Symposium on VLSI Technology (VLSIT)

Year: 2012 | Conference Paper |

Cited by: Papers (10)

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In planar MOSFET, the optimization of finger length should be carried out with considering fT, fmax and flicker noise because the noise degradation at STI edge effect appears below 1μm. In FinFET, the optimization of not only finger length but also the distance between gate and source, drain contact region and fin pitch are necessary to reduce parasitic resistance and capacitance. According to our...Show More

The optimum device parameters for high RF and analog/MS performance in planar MOSFET and FinFET

T. Ohguro;Y. Higashi;K. Okano;S. Inaba;Y. Toyoshima

2012 Symposium on VLSI Technology (VLSIT)

Year: 2012 | Conference Paper |

Comprehensive understanding of random telegraph noise with

Y. Higashi;N. Momo;H. S. Momose;T. Ohguro;K. Matsuzawa

2011 Symposium on VLSI Technology - Digest of Technical Papers

Year: 2011 | Conference Paper |

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Physical modeling of transient and frequency domain noise simulation for random telegraph noise (RTN) is conducted, considering discretized traps and energy transition in insulator. The models are implemented in a 3D device simulator to consider the device structure effect and bias effect universally. Trap density and trap distribution in insulator are predicted quantitatively with comparison of m...Show More

Comprehensive understanding of random telegraph noise with

Y. Higashi;N. Momo;H. S. Momose;T. Ohguro;K. Matsuzawa

2011 Symposium on VLSI Technology - Digest of Technical Papers

Year: 2011 | Conference Paper |

A high power-handling RF MEMS tunable capacitor using quadruple series capacitor structure

H. Yamazaki;T. Ikehashi;T. Saito;E. Ogawa;T. Masunaga;T. Ohguro;Y. Sugizaki;H. Shibata

2010 IEEE MTT-S International Microwave Symposium

Year: 2010 | Conference Paper |

Cited by: Papers (1)

This paper presents an RF MEMS tunable capacitor that achieves excellent power-handling property with relatively low actuation voltage. The tunable capacitor consists of two fixed MIM (Metal-Insulator-Metal) capacitors and two MEMS capacitor elements, all connected in series. This quadruple series capacitor (QSC) structure enables to reduce the actuation voltage without sacrificing the power-handl...Show More

A high power-handling RF MEMS tunable capacitor using quadruple series capacitor structure

H. Yamazaki;T. Ikehashi;T. Saito;E. Ogawa;T. Masunaga;T. Ohguro;Y. Sugizaki;H. Shibata

2010 IEEE MTT-S International Microwave Symposium

Year: 2010 | Conference Paper |

A high power-handling RF MEMS tunable capacitor using quadruple series capacitor structure

Hiroaki Yamazaki;Tamio Ikehashi;Tomohiro Saito;Etsuji Ogawa;Takayuki Masunaga;Tatsuya Ohguro;Yoshiaki Sugizaki;Hideki Shibata

2010 IEEE MTT-S International Microwave Symposium

Year: 2010 | Conference Paper |

Cited by: Papers (13) | Patents (1)

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This paper presents an RF MEMS tunable capacitor that achieves an excellent power-handling property with relatively low actuation voltage. The tunable capacitor consists of two fixed MIM (Metal-Insulator-Metal) capacitors and two MEMS capacitor elements, all connected in series. This quadruple series capacitor (QSC) structure enables reduction of the actuation voltage without sacrificing the power...Show More

A high power-handling RF MEMS tunable capacitor using quadruple series capacitor structure

Hiroaki Yamazaki;Tamio Ikehashi;Tomohiro Saito;Etsuji Ogawa;Takayuki Masunaga;Tatsuya Ohguro;Yoshiaki Sugizaki;Hideki Shibata

2010 IEEE MTT-S International Microwave Symposium

Year: 2010 | Conference Paper |

Low profile double resonance frequency tunable antenna using RF MEMS variable capacitor for digital terrestrial broadcasting reception

Yukako Tsutsumi;Masaki Nishio;Shuichi Obayashi;Hiroki Shoki;Tamio Ikehashi;Hiroaki Yamazaki;Etsuji Ogawa;Tomohiro Saito;Tatsuya Ohguro;Tasuku Morooka

2009 IEEE Asian Solid-State Circuits Conference

Year: 2009 | Conference Paper |

Cited by: Papers (5)

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It is difficult to realize the built-in antenna for wideband systems, because a frequency bandwidth of the low profile antenna is narrow. A frequency tunable antenna is a technique for wideband characteristics. In this paper a low profile double resonance frequency tunable antenna using MEMS variable capacitors is presented. It has high efficiency over a wide frequency band. Through both resonant ...Show More

Low profile double resonance frequency tunable antenna using RF MEMS variable capacitor for digital terrestrial broadcasting reception

Yukako Tsutsumi;Masaki Nishio;Shuichi Obayashi;Hiroki Shoki;Tamio Ikehashi;Hiroaki Yamazaki;Etsuji Ogawa;Tomohiro Saito;Tatsuya Ohguro;Tasuku Morooka

2009 IEEE Asian Solid-State Circuits Conference

Year: 2009 | Conference Paper |

Analysis of Fin width and temperature dependence of flicker noise for bulk-FinFET

T. Ohguro;K. Okano;T. Izumida;S. Inaba;N. Momo;K. Kokubun;H. S. Momose;Y. Toyoshima

2009 European Microwave Integrated Circuits Conference (EuMIC)

Year: 2009 | Conference Paper |

Cited by: Papers (1)

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In this paper, detailed analysis of Fin width and temperature dependence of flicker noise for bulk-FinFET are described. The FinFET with narrow fin width such as below 30 nm is attractive for scaled CMOS because of double gate structure. Additionally, the flicker noise of FinFET decreases and the temperature dependence of the noise become smaller as the fin width becomes narrower. According to our...Show More

Analysis of Fin width and temperature dependence of flicker noise for bulk-FinFET

T. Ohguro;K. Okano;T. Izumida;S. Inaba;N. Momo;K. Kokubun;H. S. Momose;Y. Toyoshima

2009 European Microwave Integrated Circuits Conference (EuMIC)

Year: 2009 | Conference Paper |

90nm node RF CMOS technology with latch-up immunity on high-resistivity substrate

N. Momo;Y. Higashi;M. Oda;K. Matsuzawa;K. Kokubun;T. Ohguro;H. S. Momose;Y. Toyoshima

2009 European Microwave Integrated Circuits Conference (EuMIC)

Year: 2009 | Conference Paper |

Cited by: Papers (1)

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This paper presents a detailed analysis of latch-up characteristics for 90 nm RF CMOS on high-resistivity substrate with 400 ohm-cm for the first time. According to our measurement and simulation results, latch-up dependence of PNP base and NPN emitter injection mode on Si substrate resistivity is small. On the other hand, PNP emitter and NPN base injection modes are sensitive to the resistivity b...Show More

90nm node RF CMOS technology with latch-up immunity on high-resistivity substrate

N. Momo;Y. Higashi;M. Oda;K. Matsuzawa;K. Kokubun;T. Ohguro;H. S. Momose;Y. Toyoshima

2009 European Microwave Integrated Circuits Conference (EuMIC)

Year: 2009 | Conference Paper |

Highly reliable and manufacturable in-line wafer-level hermetic packages for RF MEMS variable capacitor

Akihiro Kojima;Yoshiaki Shimooka;Yoshiaki Sugizaki;Mitsuyoshi Endo;Hiroaki Yamazaki;Etsuji Ogawa;Tamio Ikehashi;Tatsuya Ohguro;Susumu Obata;Takeshi Miyagi;Ikuo Mori;Yoshiaki Toyoshima;Hideki Shibata

TRANSDUCERS 2009 - 2009 International Solid-State Sensors, Actuators and Microsystems Conference

Year: 2009 | Conference Paper |

Cited by: Papers (6)

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In this paper, we report a thin-film encapsulation technology for wafer-level microelectromechanical systems (MEMS) variable capacitor package. The electrical characteristics of MEMS are adversely affected by moisture. In order to prevent moisture from permeating into a package, the top surface was protected with a plasma-enhanced chemical vapor deposition (PE-CVD) SiN layer. The developed package...Show More

Highly reliable and manufacturable in-line wafer-level hermetic packages for RF MEMS variable capacitor

Akihiro Kojima;Yoshiaki Shimooka;Yoshiaki Sugizaki;Mitsuyoshi Endo;Hiroaki Yamazaki;Etsuji Ogawa;Tamio Ikehashi;Tatsuya Ohguro;Susumu Obata;Takeshi Miyagi;Ikuo Mori;Yoshiaki Toyoshima;Hideki Shibata

TRANSDUCERS 2009 - 2009 International Solid-State Sensors, Actuators and Microsystems Conference

Year: 2009 | Conference Paper |

An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation

Tamio Ikehashi;Takayuki Miyazaki;Hiroaki Yamazaki;Atsushi Suzuki;Etsuji Ogawa;Shinji Miyano;Tomohiro Saito;Tatsuya Ohguro;Takeshi Miyagi;Yoshiaki Sugizaki;Nobuaki Otsuka;Hideki Shibata;Yoshiaki Toyoshima

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

Year: 2008 | Conference Paper |

Cited by: Papers (18) | Patents (2)

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We propose an IBA scheme based on a pull-out detection, which is suitable for implementing in a circuit. The scheme is implemented in a driver IC that is part of a module with an RF MEMS variable capacitor. No failures are observed over 108 cycles at 85degC, which is an accelerated charging condition.Show More

An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation

Tamio Ikehashi;Takayuki Miyazaki;Hiroaki Yamazaki;Atsushi Suzuki;Etsuji Ogawa;Shinji Miyano;Tomohiro Saito;Tatsuya Ohguro;Takeshi Miyagi;Yoshiaki Sugizaki;Nobuaki Otsuka;Hideki Shibata;Yoshiaki Toyoshima

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

Year: 2008 | Conference Paper |

Process dependence of 0.11 μm RF CMOS on high-resistivity substrate for System on Chip (SOC) application

T. Ohguro;K. Kojima;N. Momo;H. S. Momose;Y. Toyoshima

2008 IEEE Radio Frequency Integrated Circuits Symposium

Year: 2008 | Conference Paper |

Cited by: Papers (1)

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High-resistivity substrate with beyond 1000 ohm-cm realizes high performance in terms of inductor, antenna, MIM capacitor and substrate noise for high- frequency applications. However, this wafer has serious problems for mixed-signal, RF and digital circuits. Those are reduction of high resistivity during sinter process such as 400degC, larger leakage current between nwells, extreme lower snap-bac...Show More

Process dependence of 0.11 μm RF CMOS on high-resistivity substrate for System on Chip (SOC) application

T. Ohguro;K. Kojima;N. Momo;H. S. Momose;Y. Toyoshima

2008 IEEE Radio Frequency Integrated Circuits Symposium

Year: 2008 | Conference Paper |

A 3V Operation RF MEMS Variable Capacitor using Piezoelectric and Electrostatic Actuation with Lithographical Bending Control

T. Ikehashi;E. Ogawa;H. Yamazaki;T. Ohguro

TRANSDUCERS 2007 - 2007 International Solid-State Sensors, Actuators and Microsystems Conference

Year: 2007 | Conference Paper |

Cited by: Papers (2)

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A 3 V operation RF MEMS variable capacitor using hybrid actuation of piezoelectric and electrostatic forces is presented. Bending of the piezoelectric actuator is controlled by a lithographical pattern formed on top of the actuator. The hybrid actuation and the optimized bending enabled 2.6 V pull- in voltage with the pull-out voltage as high as 2.0 V The measured capacitance ratio is 14.Show More

A 3V Operation RF MEMS Variable Capacitor using Piezoelectric and Electrostatic Actuation with Lithographical Bending Control

T. Ikehashi;E. Ogawa;H. Yamazaki;T. Ohguro

TRANSDUCERS 2007 - 2007 International Solid-State Sensors, Actuators and Microsystems Conference

Year: 2007 | Conference Paper |

Electrical Characteristics in N- and P-MOSFETS with Slightly Tilted Off-Axis (110) Channel

H. S. Momose;S. Yoshitomi;K. Kojima;T. Ohguro;Y. Toyoshima;H. Ishiuchi

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems

Year: 2007 | Conference Paper |

Cited by: Papers (2)

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Si surface properties and electrical characteristics in n- and p-MOSFETs with 2-6 degree tilted off-axis (110) channel were investigated for the first time. The transconductance of p-MOSFET with off-axis channel was significantly degraded than that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved than that of normal channel. The changes were larger than those observ...Show More

Electrical Characteristics in N- and P-MOSFETS with Slightly Tilted Off-Axis (110) Channel

H. S. Momose;S. Yoshitomi;K. Kojima;T. Ohguro;Y. Toyoshima;H. Ishiuchi

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems

Year: 2007 | Conference Paper |

STARC's Semiconductor Design Technology Research Activities and the HiSIM2 Advanced MOSFET Model Project

Y. Furui;M. Miura-Mattausch;N. Sadachika;M. Miyake;T. Ezaki;H.J. Mattausch;T. Ohguro;T. Iizuka;R. Inagaki;N. Fudanuki

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems

Year: 2007 | Conference Paper |

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STARC (Semiconductor Technology Academic Research Center) is a research consortium co-founded by major Japanese semiconductor companies, whose mission is to contribute to the growth of the Japanese semiconductor industry by developing leading-edge SoC design technologies. One of the achievements enabled by the academia collaboration is HiSIM (Hiroshima University STARC IGFET Model) an advanced MOS...Show More

STARC's Semiconductor Design Technology Research Activities and the HiSIM2 Advanced MOSFET Model Project

Y. Furui;M. Miura-Mattausch;N. Sadachika;M. Miyake;T. Ezaki;H.J. Mattausch;T. Ohguro;T. Iizuka;R. Inagaki;N. Fudanuki

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems

Year: 2007 | Conference Paper |

Noise Modeling Based on Self-Consistent Surface-Potential Description for Advanced MOSFETs aiming at RF Applications

T. Ezaki;T. Warabino;M. Miyake;N. Sadachika;D. Navarro;H. J. Mattausch;M. Miura-Mattausch;T. Ohguro;T. Iizuka;M. Taguchi;S. Kumashiro;S. Miyamoto

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings

Year: 2006 | Conference Paper |

Cited by: Papers (1)

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We have developed MOSFETs noise models for the 1/f, thermal and induced-gate noise based on self-consistent surface-potential description. Consideration of non-uniform mobility and carrier distributions arising from the surface potential distribution along the channel is indispensable for accurate noise modeling for RF applications. The developed noise models are implemented in the complete surfac...Show More

Noise Modeling Based on Self-Consistent Surface-Potential Description for Advanced MOSFETs aiming at RF Applications

T. Ezaki;T. Warabino;M. Miyake;N. Sadachika;D. Navarro;H. J. Mattausch;M. Miura-Mattausch;T. Ohguro;T. Iizuka;M. Taguchi;S. Kumashiro;S. Miyamoto

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings

Year: 2006 | Conference Paper |

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