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Model-Based Development to Improve Electrical and Thermal Performances for Robust Si Power MOSFETs Using Embedded Die Packaging Technology
Kentaro Mori;Kohei Oasa;Hitoshi Imi;Yutaro Hayashi;Tatsuya Ohguro;Tatsuya Nishiwaki;Fumiyoshi Kawashiro
2024 IEEE 10th Electronics System-Integration Technology Conference (ESTC)
Year: 2024 | Conference Paper |
In this study, embedded die packaging technology was used to evaluate device characteristics and package-level reliability tests of 40V-rated Si MOSFETs for automotive applications. Initially, electrical and thermal simulations were performed to optimize the package design, followed by fabrication of a prototype package under optimal conditions. These results showed that increasing the number of l...Show More
On-Resistance Measurements of Low Voltage MOSFET at wafer level
Kohei Oasa;Tatsuya Nishiwaki;Tatsuya Ohguro;Yasunobu Saito;Yusuke Kawaguchi
2023 35th International Conference on Microelectronic Test Structure (ICMTS)
Year: 2023 | Conference Paper |
To accelerate the development of low voltage MOSFET, we designed a test element group pattern that enables on-resistance measurement at wafer level. We confirmed that the on-resistance can be measured at wafer level by optimizing the device size and contact method to eliminate the influence of parasitic resistance.Show More
100-V Class Two-step-oxide Field-Plate Trench MOSFET to Achieve Optimum RESURF Effect and Ultralow On-resistance
Kenya Kobayashi;Hiroaki Kato;Toshifumi Nishiguchi;Saya Shimomura;Tetsuya Ohno;Tatsuya Nishiwaki;Kikuo Aida;Kentaro Ichinoseki;Kohei Oasa;Yusuke Kawaguchi
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)
Year: 2019 | Conference Paper |
Cited by: Papers (17)
We propose a 100-V class two-step-oxide Field-Plate MOSFET (2-step FP-MOSFET), which is formed by two steps of thick-oxide to simplify the structure and fabrication process. By optimizing design parameters, we reveal the 2-step FP-MOSFET can achieve sufficient RESURF (Reduced Surface Field) effect and an ultralow specific on-resistance ( RONA). Measurement results showed breakdown voltage of 109.9...Show More
Alpha-Particle Shielding Effect of Thick Copper Plating Film on Power MOSFETs
Tatsuya Nishiwaki;Kohei Oasa;Kentaro Ichinoseki;Kikuo Aida;Tatsuya Ohguro;Yoshiharu Takada;Hideharu Kojima;Yusuke Kawaguchi
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)
Year: 2019 | Conference Paper |
Cited by: Papers (4)
We investigated characteristics impact of alpha-particles irradiation to power MOSFETs and demonstrated alpha-particle shielding effect of thick copper plating film on a power MOSFET. We used americium-241 alpha-source for irradiating alpha-particles to the surface of the power MOSFET die. Irradiation under gate-source bias caused threshold voltage (Vth) decrease due to generated trapped holes in ...Show More
Evaluation methodology for current collapse phenomenon of GaN HEMTs
Toru Sugiyama;Kohei Oasa;Yasunobu Saito;Akira Yoshioka;Takuo Kikuchi;Aya Shindome;Tatsuya Ohguro;Takeshi Hamamoto
2018 IEEE International Reliability Physics Symposium (IRPS)
Year: 2018 | Conference Paper |
Cited by: Papers (2)
Methods of both evaluation and analysis of current collapse (C/C) in GaN HEMTs are discussed. Recently, guidelines to the methods of evaluation of C/C in comparing device characteristics have been required as the increase in on-resistance resulting from C/C depends significantly on stress conditions and the applied method. Therefore, as a guideline, we propose the DC voltage stress and inductance ...Show More
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