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Chenglin Bai - IEEE Xplore Author Profile

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Author details

Chenglin Bai

Also published under: Chenlin Bai

Publications

50

Citations

205

Publications by Year

20112025

Co-Authors:

Wanxiang BiYanfeng BiLingguo CaoMinghua CaoNan-Kuang Chen

Show All Co-Authors (118)

Chenglin Bai

Also published under: Chenlin Bai

Affiliation

School of Physics Science and Information Engineering

Liaocheng University

Liaocheng, China

Publication Topics

Additive Noise,
Constellation Points,
Standard Single-mode Fiber,
Optical Bandpass Filter,
Forward Error Correction,
Phase Noise,
Probabilistic Shaping,
Quadrature Amplitude Modulation,
Simulation Results,
Amplified Spontaneous Emission,
Bias Voltage,
Bit Error Rate

Biography

Chenglin Bai is a second-class Professor. He has authored more than 100 academic papers indexed by SCI and EI and has also authored monographs.,He was awarded the second prize of outstanding scientific research achievement award (science and technology progress award), two second prize of Shandong Science and Technology Award (natural science award), one third prize, and 2 third prize of Shandong Science and Technology Progress Award.(Based on document published on 4 February 2020).

Publications

50

Citations

205

Publications by Year

20112025

Co-Authors:

Wanxiang Bi
Yanfeng Bi
Lingguo Cao
Minghua Cao
Nan-Kuang Chen

Show All Co-Authors (118)

Author's Published Works

Search History

Showing 1-13 of 13 results

Conferences (9)

Journals (4)

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Suhwan Lim(13)
Jongho Woo(13)
Daewon Ha(13)
Wanki Kim(13)
Kwangsoo Kim(12)
Institute of Materials, Georgia Institute of Technology, Atlanta, GA, USA(2)
Semiconductor R&D Center, Samsung Electronics Co., Ltd, South Korea(2)
School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA(2)
Institute of Electronics and Nanotechnology, Georgia Institute of Technology, Atlanta, GA, USA(2)
School of Electrical and Computer Engineering and the School of Material Science and Engineering, Georgia Institute of Technology, Atlanta, GA, USA(2)
2024 IEEE International Electron Devices Meeting (IEDM)(4)
IEEE Electron Device Letters(3)
2024 IEEE International Reliability Physics Symposium (IRPS)(2)
2023 International Electron Devices Meeting (IEDM)(1)
2024 IEEE International Memory Workshop (IMW)(1)
IEEE(13)
San Francisco, CA, USA(5)
Grapevine, TX, USA(2)
Honolulu, HI, USA(1)
Seoul, Korea, Republic of(1)
Gate Stack(11)
Charge Trapping(10)
Memory Window(9)
Ferroelectric Layer(8)
Ferroelectric Field-effect Transistor(6)

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Demonstration of Robust Retention in Band Engineered FEFETs for NAND Storage Applications Using Tunnel Dielectric Layer

Prasanna Venkatesan;Lance Fernandes;Priyankka Ravikumar;Chinsung Park;Huy Tran;Zekai Wang;Hari Jayasankar;Amrit Garlapati;Taeyoung Song;Mengkun Tian;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Shimeng Yu;Suman Datta;Wanki Kim;Daewon Ha;Asif Khan

IEEE Electron Device Letters

Year: 2025 | Volume: 46, Issue: 3 | Journal Article |

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We perform a comprehensive study of memory retention characteristics in ferroelectric field-effect transistors with different engineered gate stacks designed to achieve a large memory window (MW) for NAND storage applications. Through this study, we show that the widely reported retention loss in these band-engineered FEFETs can be mitigated by optimizing the position of the dielectric insert. Spe...Show More

Demonstration of Robust Retention in Band Engineered FEFETs for NAND Storage Applications Using Tunnel Dielectric Layer

Prasanna Venkatesan;Lance Fernandes;Priyankka Ravikumar;Chinsung Park;Huy Tran;Zekai Wang;Hari Jayasankar;Amrit Garlapati;Taeyoung Song;Mengkun Tian;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Shimeng Yu;Suman Datta;Wanki Kim;Daewon Ha;Asif Khan

IEEE Electron Device Letters

Year: 2025 | Volume: 46, Issue: 3 | Journal Article |

Optimizing Memory Window for Ferroelectric Nand Applications: An Experimental Study on Dielectric Material Selection and Layer Positioning

Lance Fernandes;Prasanna Venkatesan Ravindran;Jiayi Chen;Mengkun Tian;Dipjyoti Das;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Shimeng Yu;Suman Datta;Asif Khan

IEEE Transactions on Electron Devices

Year: 2025 | Volume: 72, Issue: 1 | Journal Article |

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We present an experimental study optimizing a band-engineered gate-stack by incorporating both a tunnel dielectric layer (TDL) and a gate blocking layer (GBL) for ferroelectric (FE) nand flash applications, with a total thickness budget of 18 nm. Using Hf

$_{{0}.{5}}$ Zr

$_{{0}.{5}}$ O2 (HZO) as the FE material, we explore Al2O3, SiO2, Si3N4, and HfO2 as TDL and GBL materials. By systematically va...Show More

Optimizing Memory Window for Ferroelectric Nand Applications: An Experimental Study on Dielectric Material Selection and Layer Positioning

Lance Fernandes;Prasanna Venkatesan Ravindran;Jiayi Chen;Mengkun Tian;Dipjyoti Das;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Shimeng Yu;Suman Datta;Asif Khan

IEEE Transactions on Electron Devices

Year: 2025 | Volume: 72, Issue: 1 | Journal Article |

Oxide Channel Ferroelectric NAND Device with Source-Tied Covering Metal Structure: Wide Memory Window (14.3 V), Reliable Retention (> 10 Years) and Disturbance Immunity $(\Delta \mathrm{V}_{\text{th}}\leq 0.1\mathrm{V})$ for QLC Operation

Hongrae Joh;Giuk Kim;Jihye Ock;Seungyeob Kim;Sangmok Lee;Sangho Lee;Kwangsoo Kim;Suhwan Lim;Jongho Woo;Wanki Kim;Daewon Ha;Jinho Ahn;Sanghun Jeon

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

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We show an oxide-channel (Ox. Ch.) based gate-injection type ferroelectric NAND (FeNAND) device with source-tied covering metal (SCM) and control dielectric (C.DE). The SCM and C.DE play crucial roles in the performance enhancement of FeNAND cells. (i) The proposed structure addresses the channel depletion issue of Ox.Ch. by utilizing accumulated holes in the grounded SCM during ERS. This increase...Show More

Oxide Channel Ferroelectric NAND Device with Source-Tied Covering Metal Structure: Wide Memory Window (14.3 V), Reliable Retention (> 10 Years) and Disturbance Immunity $(\Delta \mathrm{V}_{\text{th}}\leq 0.1\mathrm{V})$ for QLC Operation

Hongrae Joh;Giuk Kim;Jihye Ock;Seungyeob Kim;Sangmok Lee;Sangho Lee;Kwangsoo Kim;Suhwan Lim;Jongho Woo;Wanki Kim;Daewon Ha;Jinho Ahn;Sanghun Jeon

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

Clarifying the Role of Ferroelectric in Expanding the Memory Window of Ferroelectric FETs with Gate-Side Injection: Isolating Contributions from Polarization and Charge Trapping

Yixin Qin;Saikat Chakraborty;Zijian Zhao;Kijoon Kim;Suhwan Lim;Jongho Woo;Kwangsoo Kim;Wanki Kim;Daewon Ha;Xiao Gong;Asif Khan;Vijaykrishnan Narayanan;Jaydeep P. Kulkarni;Kai Ni

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

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In this work, we performed a comprehensive experimental and modeling study, clarifying the role of ferroelectric materials in boosting the memory window of FeFETs with gate-side charge injection for the first time. We separated the ferroelectric contributions to the memory window into remnant polarization and top charge trap layer (CTL) trapping. Our findings demonstrate that: (i) Ferroelectric ma...Show More

Clarifying the Role of Ferroelectric in Expanding the Memory Window of Ferroelectric FETs with Gate-Side Injection: Isolating Contributions from Polarization and Charge Trapping

Yixin Qin;Saikat Chakraborty;Zijian Zhao;Kijoon Kim;Suhwan Lim;Jongho Woo;Kwangsoo Kim;Wanki Kim;Daewon Ha;Xiao Gong;Asif Khan;Vijaykrishnan Narayanan;Jaydeep P. Kulkarni;Kai Ni

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

Unveiling the Origin of Disturbance in FeFET and the Potential of Multifunctional TiO2 as a Breakthrough for Disturb-Free 3D NAND Cell: Experimental and Modeling

Giuk Kim;Hyunjun Kang;Sangho Lee;Hyojun Choi;Yangjin Jung;Mincheol Shin;Kwangsoo Kim;Suhwan Lim;Jongho Woo;Wanki Kim;Daewon Ha;Jinho Ahn;Sanghun Jeon

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

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We reveal the origin of disturbance issues in ferroelectric FETs (FeFETs) with a metal-gate interlayer (G.IL)-ferroelectric (FE)-channel interlayer (Ch.IL)-Si (MIFIS) stack. To achieve both low-voltage operation and disturbance immunity, we introduce a multi-functional

$\text{TiO}_{2}$ layer, positioned between the G.IL and FE layer.

$\text{TiO}_{2}$ multi-functional layer (MFL) serves two pivotal...Show More

Unveiling the Origin of Disturbance in FeFET and the Potential of Multifunctional TiO2 as a Breakthrough for Disturb-Free 3D NAND Cell: Experimental and Modeling

Giuk Kim;Hyunjun Kang;Sangho Lee;Hyojun Choi;Yangjin Jung;Mincheol Shin;Kwangsoo Kim;Suhwan Lim;Jongho Woo;Wanki Kim;Daewon Ha;Jinho Ahn;Sanghun Jeon

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

Gate-stack Optimization to Mitigate the Cylindrical Effect in Ferroelectric VNAND

Kwangsoo Kim;Suhwan Lim;Jongho Woo;Junyeong Lim;Sijung Yoo;Hyoseok Kim;Jaewoo Park;Haeyeon Jun;Seunghyun Kim;Myunghun Woo;Taeyoung Kim;Sanghyun Park;Hanseung Ko;Youngji Noh;Moonkang Choi;Jongyeon Baek;Jisung Kim;Kiheun Lee;Sam Park;Dukhyun Choe;Moonyoung Jung;Gukhyon Yon;Suhyeong Lee;Hyung Joon Kim;Kijoon Kim;Sungduk Hong;Kwangmin Park;Bong Jin Kuh;Wanki Kim;Daewon Ha;Sujin Ahn;Jaihyuk Song

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

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For the first time, we demonstrate an in-depth analysis on a novel multi-layered gate-interfacial-layer (G.IL) and high-k channel-interfacial-layer (Ch.IL) in metal-insulator-ferroelectric-insulator-silicon (MIFIS) gate stack FeFETs, using simulations and experimental validation. By exploring materials with varying energy barrier heights between the gate metal and G.IL to control the tunneling of ...Show More

Gate-stack Optimization to Mitigate the Cylindrical Effect in Ferroelectric VNAND

Kwangsoo Kim;Suhwan Lim;Jongho Woo;Junyeong Lim;Sijung Yoo;Hyoseok Kim;Jaewoo Park;Haeyeon Jun;Seunghyun Kim;Myunghun Woo;Taeyoung Kim;Sanghyun Park;Hanseung Ko;Youngji Noh;Moonkang Choi;Jongyeon Baek;Jisung Kim;Kiheun Lee;Sam Park;Dukhyun Choe;Moonyoung Jung;Gukhyon Yon;Suhyeong Lee;Hyung Joon Kim;Kijoon Kim;Sungduk Hong;Kwangmin Park;Bong Jin Kuh;Wanki Kim;Daewon Ha;Sujin Ahn;Jaihyuk Song

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

Disturb and its Mitigation in Ferroelectric Field-Effect Transistors With Large Memory Window for NAND Flash Applications

Prasanna Venkatesan;Chinsung Park;Taeyoung Song;Lance Fernandes;Dipjyoti Das;Nashrah Afroze;Priyankka Gundlapudi Ravikumar;Mengkun Tian;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Souvik Mahapatra;Shimeng Yu;Suman Datta;Asif Khan

IEEE Electron Device Letters

Year: 2024 | Volume: 45, Issue: 12 | Journal Article |

Cited by: Papers (1)

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We study the disturb characteristics of ferroelectric field-effect transistors (FEFETs) with band-engineered gate stacks. We demonstrate that integrating a dielectric Al2O3 layer within the ferroelectric (FE) Hf

$_{{0}.{5}}$ Zr

$_{{0}.{5}}$ O2 layer in the gate stack significantly enhances the memory window (MW), achieving levels suitable for quad-level cell operation (approximately 7.5 V) while o...Show More

Disturb and its Mitigation in Ferroelectric Field-Effect Transistors With Large Memory Window for NAND Flash Applications

Prasanna Venkatesan;Chinsung Park;Taeyoung Song;Lance Fernandes;Dipjyoti Das;Nashrah Afroze;Priyankka Gundlapudi Ravikumar;Mengkun Tian;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Souvik Mahapatra;Shimeng Yu;Suman Datta;Asif Khan

IEEE Electron Device Letters

Year: 2024 | Volume: 45, Issue: 12 | Journal Article |

In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND Beyond 1K Layers: Experimental Demonstration and Modeling

Giuk Kim;Hyojun Choi;Hunbeom Shin;Sangho Lee;Sangmok Lee;Yunseok Nam;Minhyun Jung;Ilho Myeong;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Jinho Ahn;Sanghun Jeon

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Year: 2024 | Conference Paper |

Cited by: Papers (2)

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In this work, we experimentally demonstrate a remarkable performance improvement, boosted by the interaction of charge trapping & ferroelectric (FE) switching effects in metal-band engineered gate interlayer (BE-G.IL)- FE-channel interlayer (Ch.IL)-Si (MIFIS) FeFET. The MIFIS with BE-G.IL (BE-MIFIS) facilitates the maximized ‘positive feedback’ (Posi. FB.) of dual effects, leading to low operation...Show More

In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND Beyond 1K Layers: Experimental Demonstration and Modeling

Giuk Kim;Hyojun Choi;Hunbeom Shin;Sangho Lee;Sangmok Lee;Yunseok Nam;Minhyun Jung;Ilho Myeong;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Jinho Ahn;Sanghun Jeon

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Year: 2024 | Conference Paper |

Material Choices for Tunnel Dielectric Layer and Gate Blocking Layer for Ferroelectric NAND Applications

Lance Fernandes;Prasanna Venkatesan Ravindran;Taeyoung Song;Dipjyoti Das;Chinsung Park;Nashrah Afroze;Mengkun Tian;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Shimeng Yu;Suman Datta;Asif Khan

IEEE Electron Device Letters

Year: 2024 | Volume: 45, Issue: 10 | Journal Article |

Cited by: Papers (4)

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We present an experimental study to compare the impacts of different dielectric materials - Al2O3 and SiO2 used as the tunnel dielectric layer (TDL) and the gate blocking layer (GBL) on the performance of ferroelectric gate stacks for NAND storage applications. We considered the maximum memory window (MW) and the incremental step program pulse (ISPP) slope as the key performance metrics. In a gate...Show More

Material Choices for Tunnel Dielectric Layer and Gate Blocking Layer for Ferroelectric NAND Applications

Lance Fernandes;Prasanna Venkatesan Ravindran;Taeyoung Song;Dipjyoti Das;Chinsung Park;Nashrah Afroze;Mengkun Tian;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Shimeng Yu;Suman Datta;Asif Khan

IEEE Electron Device Letters

Year: 2024 | Volume: 45, Issue: 10 | Journal Article |

Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation

Dipjyoti Das;Lance Fernandes;Prasanna Venkatesan Ravindran;Taeyoung Song;Chinsung Park;Nashrah Afroze;Mengkun Tian;Hang Chen;Winston Chem;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Shimeng Yu;Suman Datta;Asif Khan

2024 IEEE International Memory Workshop (IMW)

Year: 2024 | Conference Paper |

Cited by: Papers (3)

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We report a framework for designing a ferroelectric gate stack for vertical NAND with efficient multi-bit performance by evaluating various gate stacks, including those with a tunnel dielectric layer (TDL), a gate blocking layer (GBL), different post-metallization annealing (PMA) temperatures and nanolaminates. Using the Memory Window (MW) slope as the primary design metric, our study reveals that...Show More

Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation

Dipjyoti Das;Lance Fernandes;Prasanna Venkatesan Ravindran;Taeyoung Song;Chinsung Park;Nashrah Afroze;Mengkun Tian;Hang Chen;Winston Chem;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Shimeng Yu;Suman Datta;Asif Khan

2024 IEEE International Memory Workshop (IMW)

Year: 2024 | Conference Paper |

Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET

Taeyoung Kim;Suhwan Lim;Ilho Myeong;Sanghyun Park;Suseong Noh;Seung Min Lee;Jongho Woo;Hanseung Ko;Youngji Noh;Moonkang Choi;Kiheun Lee;Sangwoo Han;Jongyeon Baek;Kijoon Kim;Dongjin Jung;Ji-sung Kim;Jaewoo Park;Seunghyun Kim;Hyoseok Kim;Sijung Yoo;Hyun Jae Lee;Duk-Hyun Choe;Seung-Geol Nam;Ilyoung Yoon;Chaeho Kim;Kwanzsoo Kim;Kwanzmin Park;Bong Jin Kuh;Jinseong Heo;Wanki Kim;Daewon Ha;Jaihyuk Song

2024 IEEE International Reliability Physics Symposium (IRPS)

Year: 2024 | Conference Paper |

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For the first time, we investigate a drain current (read current) degradation in Ferroelectric field effect transistor (Fe-FET). This phenomenon is due to trapping/de-trapping charge rather than charged remnant polarization (Pr) of ferroelectric layer. That is explained as a de-trapped compensation charge from the channel-side interfacial layer (IL), and a trapped charge from substrate silicon cha...Show More

Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET

Taeyoung Kim;Suhwan Lim;Ilho Myeong;Sanghyun Park;Suseong Noh;Seung Min Lee;Jongho Woo;Hanseung Ko;Youngji Noh;Moonkang Choi;Kiheun Lee;Sangwoo Han;Jongyeon Baek;Kijoon Kim;Dongjin Jung;Ji-sung Kim;Jaewoo Park;Seunghyun Kim;Hyoseok Kim;Sijung Yoo;Hyun Jae Lee;Duk-Hyun Choe;Seung-Geol Nam;Ilyoung Yoon;Chaeho Kim;Kwanzsoo Kim;Kwanzmin Park;Bong Jin Kuh;Jinseong Heo;Wanki Kim;Daewon Ha;Jaihyuk Song

2024 IEEE International Reliability Physics Symposium (IRPS)

Year: 2024 | Conference Paper |

A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND

Ilho Myeong;Suhwan Lim;Taeyoung Kim;Sanghyun Park;Suseong Noh;Seung Min Lee;Jongho Woo;Hanseung Ko;Youngji Noh;Munkang Choi;Kiheun Lee;Sangwoo Han;Jongyeon Baek;Kijoon Kim;Dongjin Jung;Jisung Kim;Jaewoo Park;Seunghyun Kim;Hyoseok Kim;Ilyounz Yoon;Jaeho Kim;Kwangsoo Kim;Kwangmin Park;Bong Jin Kuh;Wanki Kim;Daewon Ha;Sujin Ahn;Jaihyuk Song;Sijung Yoo;Hyun Jae Lee;Duk-Hyun Choe;Seung-Geol Nam;Jinseong Heo

2024 IEEE International Reliability Physics Symposium (IRPS)

Year: 2024 | Conference Paper |

Cited by: Papers (3)

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Read-After-Write-Delay (RAWD) is an important show-stopper (S.S) in ferroelectric based VNAND (Fe-VNAND) because the read speed is fundamentally limited by neutralization time of trapped charges between the ferroelectric layer and the interfacial oxide layer. We investigated the RAWD time (tRAWD) in Metal-Ferro-Insulator-Silicon (MFIS) gate stack and extended the analysis to Laminate-MFIS (LaMFIS)...Show More

A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND

Ilho Myeong;Suhwan Lim;Taeyoung Kim;Sanghyun Park;Suseong Noh;Seung Min Lee;Jongho Woo;Hanseung Ko;Youngji Noh;Munkang Choi;Kiheun Lee;Sangwoo Han;Jongyeon Baek;Kijoon Kim;Dongjin Jung;Jisung Kim;Jaewoo Park;Seunghyun Kim;Hyoseok Kim;Ilyounz Yoon;Jaeho Kim;Kwangsoo Kim;Kwangmin Park;Bong Jin Kuh;Wanki Kim;Daewon Ha;Sujin Ahn;Jaihyuk Song;Sijung Yoo;Hyun Jae Lee;Duk-Hyun Choe;Seung-Geol Nam;Jinseong Heo

2024 IEEE International Reliability Physics Symposium (IRPS)

Year: 2024 | Conference Paper |

Comprehensive Design Guidelines of Gate Stack for QLC and Highly Reliable Ferroelectric VNAND

Suhwan Lim;Taeyoung Kim;Ilho Myeong;Sanghyun Park;Suseong Noh;Seung Min Lee;Jongho Woo;Hanseung Ko;Youngji Noh;Moonkang Choi;Kiheun Lee;Sangwoo Han;Jongyeon Baek;Kijoon Kim;Juhyung Kim;Dongjin Jung;Kwangsoo Kim;Sijung Yoo;Hyun Jae Lee;Seung-Geol Nam;Ji-Sung Kim;Jaewoo Park;Chaeho Kim;Seunghyun Kim;Hyoseok Kim;Jinseong Heo;Kwangmin Park;Sanghun Jeon;Wanki Kim;Daewon Ha;Yu Gyun Shin;Jaihyuk Song

2023 International Electron Devices Meeting (IEDM)

Year: 2023 | Conference Paper |

Cited by: Papers (22)

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For the first time, a comprehensive guideline is proposed for a gate stack design of ferroelectric vertical NAND (Fe-VNAND), based on in-depth analytical modeling and experiments. Based on the guideline, the metal-insulator-ferroelectric (FE)-insulator-silicon (MIFIS) gate stack has been demonstrated, showcasing its benefits in all three aspects of reliability (endurance, retention, and disturb ch...Show More

Comprehensive Design Guidelines of Gate Stack for QLC and Highly Reliable Ferroelectric VNAND

Suhwan Lim;Taeyoung Kim;Ilho Myeong;Sanghyun Park;Suseong Noh;Seung Min Lee;Jongho Woo;Hanseung Ko;Youngji Noh;Moonkang Choi;Kiheun Lee;Sangwoo Han;Jongyeon Baek;Kijoon Kim;Juhyung Kim;Dongjin Jung;Kwangsoo Kim;Sijung Yoo;Hyun Jae Lee;Seung-Geol Nam;Ji-Sung Kim;Jaewoo Park;Chaeho Kim;Seunghyun Kim;Hyoseok Kim;Jinseong Heo;Kwangmin Park;Sanghun Jeon;Wanki Kim;Daewon Ha;Yu Gyun Shin;Jaihyuk Song

2023 International Electron Devices Meeting (IEDM)

Year: 2023 | Conference Paper |

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