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Demonstration of Robust Retention in Band Engineered FEFETs for NAND Storage Applications Using Tunnel Dielectric Layer
Prasanna Venkatesan;Lance Fernandes;Priyankka Ravikumar;Chinsung Park;Huy Tran;Zekai Wang;Hari Jayasankar;Amrit Garlapati;Taeyoung Song;Mengkun Tian;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Shimeng Yu;Suman Datta;Wanki Kim;Daewon Ha;Asif Khan
We perform a comprehensive study of memory retention characteristics in ferroelectric field-effect transistors with different engineered gate stacks designed to achieve a large memory window (MW) for NAND storage applications. Through this study, we show that the widely reported retention loss in these band-engineered FEFETs can be mitigated by optimizing the position of the dielectric insert. Spe...Show More
Demonstration of Robust Retention in Band Engineered FEFETs for NAND Storage Applications Using Tunnel Dielectric Layer
Prasanna Venkatesan;Lance Fernandes;Priyankka Ravikumar;Chinsung Park;Huy Tran;Zekai Wang;Hari Jayasankar;Amrit Garlapati;Taeyoung Song;Mengkun Tian;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Shimeng Yu;Suman Datta;Wanki Kim;Daewon Ha;Asif Khan
Disturb and its Mitigation in Ferroelectric Field-Effect Transistors With Large Memory Window for NAND Flash Applications
Prasanna Venkatesan;Chinsung Park;Taeyoung Song;Lance Fernandes;Dipjyoti Das;Nashrah Afroze;Priyankka Gundlapudi Ravikumar;Mengkun Tian;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Souvik Mahapatra;Shimeng Yu;Suman Datta;Asif Khan
IEEE Electron Device Letters
Cited by: Papers (1)
We study the disturb characteristics of ferroelectric field-effect transistors (FEFETs) with band-engineered gate stacks. We demonstrate that integrating a dielectric Al2O3 layer within the ferroelectric (FE) Hf _{{0}.{5}} Zr _{{0}.{5}} O2 layer in the gate stack significantly enhances the memory window (MW), achieving levels suitable for quad-level cell operation (approximately 7.5 V) while o...Show More
Disturb and its Mitigation in Ferroelectric Field-Effect Transistors With Large Memory Window for NAND Flash Applications
Prasanna Venkatesan;Chinsung Park;Taeyoung Song;Lance Fernandes;Dipjyoti Das;Nashrah Afroze;Priyankka Gundlapudi Ravikumar;Mengkun Tian;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Souvik Mahapatra;Shimeng Yu;Suman Datta;Asif Khan
Material Choices for Tunnel Dielectric Layer and Gate Blocking Layer for Ferroelectric NAND Applications
Lance Fernandes;Prasanna Venkatesan Ravindran;Taeyoung Song;Dipjyoti Das;Chinsung Park;Nashrah Afroze;Mengkun Tian;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Shimeng Yu;Suman Datta;Asif Khan
IEEE Electron Device Letters
Cited by: Papers (4)
We present an experimental study to compare the impacts of different dielectric materials - Al2O3 and SiO2 used as the tunnel dielectric layer (TDL) and the gate blocking layer (GBL) on the performance of ferroelectric gate stacks for NAND storage applications. We considered the maximum memory window (MW) and the incremental step program pulse (ISPP) slope as the key performance metrics. In a gate...Show More
Material Choices for Tunnel Dielectric Layer and Gate Blocking Layer for Ferroelectric NAND Applications
Lance Fernandes;Prasanna Venkatesan Ravindran;Taeyoung Song;Dipjyoti Das;Chinsung Park;Nashrah Afroze;Mengkun Tian;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Shimeng Yu;Suman Datta;Asif Khan
Plasma-Enhanced Atomic Layer Deposition-Based Ferroelectric Field-Effect Transistors
Chinsung Park;Prasanna Venkat Ravindran;Dipjyoti Das;Priyankka Gundlapudi Ravikumar;Chengyang Zhang;Nashrah Afroze;Lance Fernandes;Yu Hsin Kuo;Jae Hur;Hang Chen;Mengkun Tian;Winston Chern;Shimeng Yu;Asif Islam Khan
The use of the plasma-enhanced atomic layer deposition (ALD) technique for the deposition of HfO2-based ferroelectrics has received attention in recent years primarily due to wake-up free operation. However, these studies have primarily focused on metal-ferroelectric-metal (MFM) structures. In this work, we investigate the characteristics of ferroelectric field-effect transistors (FEFETs) in which...Show More
Interfacial Oxide Layer Scavenging in Ferroelectric Hf0.5Zr0.5O2-Based MOS Structures With Ge Channel for Reduced Write Voltages
Chinsung Park;Harshil Kashyap;Dipjyoti Das;Jae Hur;Nujhat Tasneem;Sarah Lombardo;Nashrah Afroze;Winston Chern;Andrew C. Kummel;Shimeng Yu;Asif Islam Khan
Strategies to reduce the interfacial oxide layer thickness in ferroelectric (FE) Hf0.5Zr0.5O2 (HZO) metal-oxide-semiconductor capacitor (FE-MOS) structures on Ge and Si substrates were investigated by electrode engineering, as means to reduce the write voltage in FE field-effect transistors (FEFETs). When the gate metal in Ge FE-MOS capacitors is changed from W (control) to Pt/Ti, the coercive vol...Show More
A Ge-Channel Ferroelectric Field Effect Transistor With Logic-Compatible Write Voltage
Dipjyoti Das;Prasanna Venkatesan Ravindran;Chinsung Park;Nujhat Tasneem;Zheng Wang;Hang Chen;Winston Chern;Shimeng Yu;Suman Datta;Asif Khan
IEEE Electron Device Letters
Cited by: Papers (9)
A major roadblock for the integration of ferroelectric-field-effect transistors (FEFETs) at advanced technology nodes for embedded memory applications is their high, logic-incompatible write voltages. Herein, we explore Ge as a channel material to reduce write voltage of FEFET and report the first demonstration of p-type Ge-FEFETs with record low write voltages of ±1.4 V with a memory window (MW) ...Show More
Characterizing HfO2-Based Ferroelectric Tunnel Junction in Cryogenic Temperature
Jae Hur;Chinsung Park;Gihun Choe;Prasanna Venkatesan Ravindran;Asif Islam Khan;Shimeng Yu
Since the discovery of ferroelectric properties in doped HfO2, various types of memory devices have emerged based on this novel material. Especially, the ferroelectric tunnel junction (FTJ) has gained considerable attention for selector-less crossbar array. Although various studies have been carried out for the HfO2-based FTJs, there are no investigations of them at a cryogenic temperature. While ...Show More
Two-phase boosted voltage generator [CMOS DRAMs]
Y.H. Kim;J.K. Nam;Y.S. Sohn;S.C. Heo;S.H. Lee;H.J. Park;Y.S. Han;J.I. Doh;Y.J. Choi;J.H. Choi;J.S. Choi;C.S. Park
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)
Year: 1999 | Conference Paper |
Cited by: Papers (1)
A two-phase boosted voltage (VPP) generator circuit was proposed for use in giga-bit DRAMs. It reduced the maximum gate oxide voltage of pass transistor and the lower limit of supply voltage to VPP and V/sub TN/ respectively while those for the conventional charge pump circuit are VPP+VDD and 1.5 V/sub TN/ respectively. Also the pumping current was increased in the new circuit.Show More
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