Jongyeon Baek

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Gate-stack Optimization to Mitigate the Cylindrical Effect in Ferroelectric VNAND

Kwangsoo Kim;Suhwan Lim;Jongho Woo;Junyeong Lim;Sijung Yoo;Hyoseok Kim;Jaewoo Park;Haeyeon Jun;Seunghyun Kim;Myunghun Woo;Taeyoung Kim;Sanghyun Park;Hanseung Ko;Youngji Noh;Moonkang Choi;Jongyeon Baek;Jisung Kim;Kiheun Lee;Sam Park;Dukhyun Choe;Moonyoung Jung;Gukhyon Yon;Suhyeong Lee;Hyung Joon Kim;Kijoon Kim;Sungduk Hong;Kwangmin Park;Bong Jin Kuh;Wanki Kim;Daewon Ha;Sujin Ahn;Jaihyuk Song

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

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For the first time, we demonstrate an in-depth analysis on a novel multi-layered gate-interfacial-layer (G.IL) and high-k channel-interfacial-layer (Ch.IL) in metal-insulator-ferroelectric-insulator-silicon (MIFIS) gate stack FeFETs, using simulations and experimental validation. By exploring materials with varying energy barrier heights between the gate metal and G.IL to control the tunneling of ...Show More

Gate-stack Optimization to Mitigate the Cylindrical Effect in Ferroelectric VNAND

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET

Taeyoung Kim;Suhwan Lim;Ilho Myeong;Sanghyun Park;Suseong Noh;Seung Min Lee;Jongho Woo;Hanseung Ko;Youngji Noh;Moonkang Choi;Kiheun Lee;Sangwoo Han;Jongyeon Baek;Kijoon Kim;Dongjin Jung;Ji-sung Kim;Jaewoo Park;Seunghyun Kim;Hyoseok Kim;Sijung Yoo;Hyun Jae Lee;Duk-Hyun Choe;Seung-Geol Nam;Ilyoung Yoon;Chaeho Kim;Kwanzsoo Kim;Kwanzmin Park;Bong Jin Kuh;Jinseong Heo;Wanki Kim;Daewon Ha;Jaihyuk Song

2024 IEEE International Reliability Physics Symposium (IRPS)

Year: 2024 | Conference Paper |

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For the first time, we investigate a drain current (read current) degradation in Ferroelectric field effect transistor (Fe-FET). This phenomenon is due to trapping/de-trapping charge rather than charged remnant polarization (Pr) of ferroelectric layer. That is explained as a de-trapped compensation charge from the channel-side interfacial layer (IL), and a trapped charge from substrate silicon cha...Show More

Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET

2024 IEEE International Reliability Physics Symposium (IRPS)

Year: 2024 | Conference Paper |

A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND

Ilho Myeong;Suhwan Lim;Taeyoung Kim;Sanghyun Park;Suseong Noh;Seung Min Lee;Jongho Woo;Hanseung Ko;Youngji Noh;Munkang Choi;Kiheun Lee;Sangwoo Han;Jongyeon Baek;Kijoon Kim;Dongjin Jung;Jisung Kim;Jaewoo Park;Seunghyun Kim;Hyoseok Kim;Ilyounz Yoon;Jaeho Kim;Kwangsoo Kim;Kwangmin Park;Bong Jin Kuh;Wanki Kim;Daewon Ha;Sujin Ahn;Jaihyuk Song;Sijung Yoo;Hyun Jae Lee;Duk-Hyun Choe;Seung-Geol Nam;Jinseong Heo

2024 IEEE International Reliability Physics Symposium (IRPS)

Year: 2024 | Conference Paper |

Cited by: Papers (3)

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Read-After-Write-Delay (RAWD) is an important show-stopper (S.S) in ferroelectric based VNAND (Fe-VNAND) because the read speed is fundamentally limited by neutralization time of trapped charges between the ferroelectric layer and the interfacial oxide layer. We investigated the RAWD time (tRAWD) in Metal-Ferro-Insulator-Silicon (MFIS) gate stack and extended the analysis to Laminate-MFIS (LaMFIS)...Show More

A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND

2024 IEEE International Reliability Physics Symposium (IRPS)

Year: 2024 | Conference Paper |

Comprehensive Design Guidelines of Gate Stack for QLC and Highly Reliable Ferroelectric VNAND

Suhwan Lim;Taeyoung Kim;Ilho Myeong;Sanghyun Park;Suseong Noh;Seung Min Lee;Jongho Woo;Hanseung Ko;Youngji Noh;Moonkang Choi;Kiheun Lee;Sangwoo Han;Jongyeon Baek;Kijoon Kim;Juhyung Kim;Dongjin Jung;Kwangsoo Kim;Sijung Yoo;Hyun Jae Lee;Seung-Geol Nam;Ji-Sung Kim;Jaewoo Park;Chaeho Kim;Seunghyun Kim;Hyoseok Kim;Jinseong Heo;Kwangmin Park;Sanghun Jeon;Wanki Kim;Daewon Ha;Yu Gyun Shin;Jaihyuk Song

2023 International Electron Devices Meeting (IEDM)

Year: 2023 | Conference Paper |

Cited by: Papers (22)

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For the first time, a comprehensive guideline is proposed for a gate stack design of ferroelectric vertical NAND (Fe-VNAND), based on in-depth analytical modeling and experiments. Based on the guideline, the metal-insulator-ferroelectric (FE)-insulator-silicon (MIFIS) gate stack has been demonstrated, showcasing its benefits in all three aspects of reliability (endurance, retention, and disturb ch...Show More

Comprehensive Design Guidelines of Gate Stack for QLC and Highly Reliable Ferroelectric VNAND

2023 International Electron Devices Meeting (IEDM)

Year: 2023 | Conference Paper |

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Jongyeon Baek

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Gate-stack Optimization to Mitigate the Cylindrical Effect in Ferroelectric VNAND

Gate-stack Optimization to Mitigate the Cylindrical Effect in Ferroelectric VNAND

Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET

Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET

A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND

A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND

Comprehensive Design Guidelines of Gate Stack for QLC and Highly Reliable Ferroelectric VNAND

Comprehensive Design Guidelines of Gate Stack for QLC and Highly Reliable Ferroelectric VNAND

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