Test Whats new message.
Scheduled Maintenance on Monday 1/13/2025
Single article sales and account management will be unavailable from 5:00 AM - 7:00 PM ET (09:00 - 23:00 UTC). We apologize for the inconvenience.
Showing 1-25 of 28 results
- Sort
Get notified when new research is published matching your search criteria.
Sort By
Results
Self-powered wearable sensor platforms for wellness
Veena Misra;Ben Calhoun;Shekhar Bhansali;John Lach;Suman Datta;Mehmet Ozturk;Alper Bozkurt;Omer Oralkan;Jason Strohmaier
2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)
Year: 2015 | Conference Paper |
Health care continues to be one of the biggest challenges facing our society. Factors such as lifestyle choices, genetics, aging, stress and environmental exposures play a critical role in determining health outcomes. Wearable technologies that can enable continuous/long-term personal health monitoring and personal environmental monitoring can empower users to make better lifestyle decisions and i...Show More
Flexible Technologies for Self-Powered Wearable Health and Environmental Sensing
Veena Misra;Alper Bozkurt;Benton Calhoun;Thomas Jackson;Jesse S. Jur;John Lach;Bongmook Lee;John Muth;Ömer Oralkan;Mehmet Öztürk;Susan Trolier-McKinstry;Daryoosh Vashaee;David Wentzloff;Yong Zhu
This article provides the latest advances from the NSF Advanced Self-powered Systems of Integrated sensors and Technologies (ASSIST) center. The work in the center addresses the key challenges in wearable health and environmental systems by exploring technologies that enable ultra-long battery lifetime, user comfort and wearability, robust medically validated sensor data with value added from mult...Show More
Tuning of the Nickel Silicide Schottky Barrier Height on p-Type Silicon by Indium Implantation
IEEE Electron Device Letters
Cited by: Papers (24)
In this letter, indium (In) implantation is introduced as a method to tune the Schottky barrier height of nickel silicide (NiSi) contacts formed on p-type silicon. Indium implantation is performed prior to NiSi formation and the implant conditions are chosen such that the implanted region is entirely consumed by the silicide. During silicide formation, some of the indium segregates at the NiSi-Si ...Show More
Schottky Barrier Height of Nickel Silicide Contacts Formed on $\hbox{Si}_{1 - x}\hbox{C}_{x}$ Epitaxial Layers
IEEE Electron Device Letters
Cited by: Papers (1)
Embedded Si1 - xCx source/drain junctions are currently considered to achieve electron mobility enhancement in nMOSFETs by inducing uniaxial tensile strain in the channel region. To utilize the mobility advantage of this technology, it is imperative to form low-resistivity contacts to Si1 - xCx alloys. In this letter, the electron and hole barrier heights at the NiSi/Si1 - xCx interface were measu...Show More
Schottky Barrier Height of Erbium Silicide on $ \hbox{Si}_{1 - x}\hbox{C}_{x}$
IEEE Electron Device Letters
Cited by: Papers (6)
In this letter, the Schottky barrier height of erbium silicide contacts formed on Si1-xCx alloys was measured. The alloys were pseudomorphically grown on Si wafers with 0% to 1.2% C occupying the substitutional sites. Schottky barrier diodes were fabricated with an ideality factor of 1.13 or less. The hole barrier height was found to be 0.73 eV independent of the C concentration. This suggests tha...Show More
Platinum Germanosilicide Contacts Formed on Strained and Relaxed $\hbox{Si}_{1 - x}\hbox{Ge}_{x}$ Layers
Emre Alptekin;Casey Joe Kirkpatrick;Veena Misra;Mehmet C. Ozturk
Contact resistivity is a key contributor to the parasitic series resistance of nanoscale MOSFETs. Since the contact resistivity is an exponential function of the Schottky barrier height, new contact materials that can provide smaller barrier heights to source-drain junctions are needed. Platinum germanosilicide (PtSi1-xGex) is of interest as a contact material to the recessed Si1-xGex junctions of...Show More
Tuning of the Platinum Silicide Schottky Barrier Height on n-Type Silicon by Sulfur Segregation
The Schottky barrier height PhiB of platinum silicide (PtSi) contacts on n-type silicon was tuned by sulfur segregation at the PtSi/Si interface. Sulfur was implanted prior to Pt deposition and segregated at the interface during PtSi formation. It was observed that the barrier height could be tuned by changing the sulfur dose. A minimum barrier height of 0.12 eV was obtained on n-type (100) Si sub...Show More
Development of plasmonics-active SERS substrates on a wafer scale for chemical and biological sensing applications
Anuj Dhawan;Yan Du;Hsinneng Wang;Donovon Leonard;Veena Misra;Mehmet Ozturk;Michael Gerhold;Tuan Vo-Dinh
2008 IEEE International Electron Devices Meeting
Year: 2008 | Conference Paper |
Cited by: Papers (3)
This paper describes the fabrication of highly efficient plasmonics-active SERS substrates - having metallic nanowire structures with pointed geometries and sub-5 nm gap between the metallic nanowires enabling concentration of high EM fields in these regions - on a wafer-scale by a reproducible process that is compatible with large-scale development of these substrates. These SERS substrates were ...Show More
Ni/sub x/Ta/sub 1-x/Si and Ni/sub x/Pt/sub 1-x/Si ternary alloys for work function tuning on SiO/sub 2/, HfSiO/sub x/ and HfO/sub 2/ dielectrics
N. Biswas;S. Novak;Bei Chen;D. Lichtenwalner;M. Ozturk;V. Misra
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.
Year: 2005 | Conference Paper |
We present two new ternary alloy silicides with tunable work function ranging between 4.27eV to 4.7eV and 4.8eV to 5.0eV respectively for dual metal gate CMOS applications. NixTa1-xSi gates were investigated for NMOS and NixPt1-xSi gates were investigated for PMOS applications on SiO2, HfO 2 and HfSiOx dielectrics. A large degree of tuning was observed on SiO2 however the tuning range decreased as...Show More
Nickel Germanosilicide contacts formed on heavily boron doped Si/sub 1-x/Ge/sub x/ source/drain junctions for nanoscale CMOS
Formation of source/drain junctions with a small parasitic series resistance is one of the key challenges for CMOS technology nodes beyond 100 nm. A new source/drain technology based on selective deposition of heavily in situ doped Si/sub 1-x/Ge/sub x/ layers was recently developed in this laboratory. This paper presents formation and structural characterization of self-aligned nickel germanosilic...Show More
In situ selectivity and thickness monitoring during selective silicon epitaxy using quadrupole mass spectrometry and wavelets
This work reports on a novel in situ sensing technique for monitoring the thickness of selectively grown Si epitaxial layers. The technique can be extended to detect selectivity loss when Si nuclei begin to appear on the insulator surface. In this technique, a quadruple mass spectrometer (QMS) monitors the ionized molecular hydrogen (H/sub 2//sup +/) signal, which is a by-product of the chemical-v...Show More
Low resistivity nickel germanosilicide contacts to ultra-shallow Si/sub 1-x/Ge/sub x/ source/drain junctions for nanoscale CMOS
IEEE International Electron Devices Meeting 2003
Year: 2003 | Conference Paper |
Selective Si/sub 1-x/Ge/sub x/ source/drain technology was previously proposed to address the parasitic series resistance requirements of future CMOS IC generations. The technology provides abrupt lateral doping profiles and high dopant activation to reduce spreading and extension resistance components of the series resistance. In addition, the smaller bandgap of Si/sub 1-x/Ge/sub x/ can provide a...Show More
Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go?
C. M. Osburn;I. Kim;S. K. Han;I. De;K. F. Yee;S. Gannavaram;S. J. Lee;C.-H. Lee;Z. J. Luo;W. Zhu;J. R. Hauser;D.-L. Kwong;G. Lucovsky;T. P. Ma;M. C. Ozturk
The vertical scaling requirements for gate stacks and for shallow extension junctions are reviewed. For gate stacks, considerable progress has been made in optimizing oxide/nitride and oxynitride dielectrics to reduce boron penetration and dielectric leakage compared to pure SiO2 in order to allow sub-2-nm dielectrics. Several promising alternative material candidates exist for 1-nm equivalent oxi...Show More
Advanced Si/sub 1-x/Gex source/drain and contact technologies for sub-70 nm CMOS
Digest. International Electron Devices Meeting,
Year: 2002 | Conference Paper |
Future CMOS technology nodes require super-abrupt source/drain junctions with very low contact resistivities. In this paper, we examine properties of ultra-shallow junctions formed by selective deposition of in-situ doped Si/sub 1-x/Ge/sub x/ alloys. Contacts to these junctions consist of self-aligned Ni and Pt germanosilicide contacts formed via solid phase reactions. We present super-abrupt junc...Show More
Ultra-shallow source/drain junctions for nanoscale CMOS using selective silicon-germanium technology
Extended Abstracts of the Second International Workshop on Junction Technology. IWJT. (IEEE Cat.No.01EX541C)
Year: 2001 | Conference Paper |
Future CMOS technology nodes bring new challenges to formation of source/drain junctions and their contacts to limit their series resistance contribution to ten percent of the device channel resistance. This requires not only extremely low junction sheet resistance values but also super abrupt doping profiles and contact resistivities that can not be obtained with the existing self-aligned silicid...Show More
Single gate 0.15 /spl mu/m CMOS devices fabricated using RTCVD in-situ boron doped Si/sub 1-x/Ge/sub x/ gates
V.Z.-Q. Li;M.R. Mirabedini;R.T. Kuehn;J.J. Wortman;M.C. Ozturk
International Electron Devices Meeting. IEDM Technical Digest
Year: 1997 | Conference Paper |
Cited by: Papers (5)
Single gate 0.15 CM CMOS devices have been successfully fabricated using in-situ boron doped polycrystalline Si/sub 1-x/Ge/sub x/ (poly-Si/sub 1-x/Ge/sub x/) as the gate material for both surface channel n- and p-MOSFETs. The p/sup +/ poly-Si/sub 1-x/Ge/sub x/ gate electrodes were deposited by rapid thermal chemical vapor deposition using a Si/sub 2/H/sub 6/, GeH/sub 4/, B/sub 2/H/sub 6/ and H/sub...Show More
Suppression of oxidation-enhanced boron diffusion in silicon by carbon implantation and characterization of MOSFETs with carbon-implanted channels
In NMOS transistors with boron-doped channels, Oxdation-Enhanced Diffusion (OED) is a key contributor to boron profile broadening. Starting with the arguments presented in several recent reports on the role of carbon in silicon as a sink for self-interstitials, we have explored the feasibility of using carbon in the Metal Oxide Silicon Field Effect Transistor (MOSFET) active region to retard boron...Show More
Suppression of oxidation enhanced boron diffusion in silicon by carbon implantation and characterization of MOSFETs with carbon implanted channels
Proceedings of 11th International Conference on Ion Implantation Technology
Year: 1996 | Conference Paper |
Scaling of MOSFETs into the deep submicron regime requires shallow doping profiles with abrupt doping transitions in the MOSFET active region. In NMOS transistors with boron doped channels, oxidation enhanced diffusion is a key contributor to boron profile broadening. Starting from the arguments presented in several recent reports on the role of carbon in silicon as a sink for self-interstitials, ...Show More
A study on channel design for 0.1 /spl mu/m buried p-channel MOSFETs
This paper investigates the channel design for buried p-channel MOSFETs with an effective channel length of 0.1 /spl mu/m via simulations using the two-dimensional device simulator PISCES IIB. A new three-layer design is considered with the objective of obtaining low junction capacitance while maintaining high current drive and suppressing punchthrough. The channel design consists of a p-type laye...Show More
Bandgap-engineered W/Si/sub 1-x/Ge/sub x//Si junctions (p/sup +/ and n/sup +/) with ultra-low contact resistivity and low leakage have been fabricated and characterized. The junctions are formed via outdiffusion from a selectively deposited Si/sub 0.7/Ge/sub 0.3/ layer which is implanted and annealed using RTA. The Si/sub 1-x/Ge/sub x/ layer can then be selectively thinned using NH/sub 4/OH/H/sub ...Show More
Ultra-low resistance W/Si/sub 1-x/Ge/sub x//Si source-drain contacts
1995 53rd Annual Device Research Conference Digest
Year: 1995 | Conference Paper |
Fabrication of CMOS devices with feature sizes on the order of 100 nm will require junction depths of less than 70 nm in order to control short-channel effects. Fully-scaled 100x100 nm/sup 2/ source-drain regions in such devices will require contact resistivities of less than 10/sup -7/ ohm-cm/sup 2/ in order not to reach limits on currents. A W contact technology was been pursued in this work. W ...Show More
Cener for advanced electronic materials processing
N.A. Masnari;J.R. Hauser;G. Lucovsky;D.M. Maher;R.J. Markunas;M.C. Ozturk;J.J. Wortman
First Page of the Article
Show MoreSelf-aligned BJTs for VLSI using a new diffusion technique for shallow base formation
A method of using selectively deposited and selectively removed 'polycrystalline' Si/sub x/Ge/sub 1-x/ as a diffusion source for the fabrication of narrow-base self-aligned BJTs (bipolar junction transistors) is described. The transistors showed excellent quality emitter-base and base-collector junction characteristics. In addition, this process was found to be completely compatible with current d...Show More
First Page of the Article
Show MoreThe heat transfer to a wafer in a rapid thermal processing (RTP) furnace is simulated by an analytical/numerical model. The model includes radiation heat transfer to the wafer from the lamps, heat conduction within the wafer, and emission of radiation from the wafer. Geometric optics are used to predict the radiant heat flux distribution over the wafer. The predicted wafer surface temperature dist...Show More
IEEE Account
Purchase Details
Profile Information
Need Help?
- US & Canada: +1 800 678 4333
- Worldwide: +1 732 981 0060
- Contact & Support
- About IEEE Xplore
- Contact Us
- Help
- Accessibility
- Terms of Use
- Nondiscrimination Policy
- Sitemap
- Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
© Copyright 2025 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.