Low resistivity nickel germanosilicide contacts to ultra-shallow Si/sub 1-x/Ge/sub x/ source/drain junctions for nanoscale CMOS

Selective Si/sub 1-x/Ge/sub x/ source/drain technology was previously proposed to address the parasitic series resistance requirements of future CMOS IC generations. The technology provides abrupt lateral doping profiles and high dopant activation to reduce spreading and extension resistance components of the series resistance. In addition, the smaller bandgap of Si/sub 1-x/Ge/sub x/ can provide a smaller metal-semiconductor barrier height, essential for low contact resistance. In this paper, we present results from an experimental study conducted on nickel germanosilicide (NiSi/sub 1-x/Ge/sub x/) contacts formed on both boron and phosphorus doped Si/sub 1-x/Ge/sub x/ alloys. It is shown that NiSi/sub 1-x/Ge/sub x/ contacts have the potential to address the contact resistance challenge of future IC generations. NiSi/sub 1-x/Ge/sub x/ contacts can be formed self-aligned to both boron and phosphorus doped Si/sub 1-x/Ge/sub x/ alloys. An extremely smooth metal-semiconductor interface can be achieved resulting in an excellent reverse leakage behavior. It is also shown that the thermal stability of NiSi/sub 1-x/Ge/sub x/ can be substantially improved by inserting a thin Pt layer under the Ni layer. On phosphorus doped Si/sub 1-x/Ge/sub x/ alloys, the lowest contact resistivity values are obtained with the Pt interlayer.

Introduction

One of the key challenges for future CMOS technology nodes is to form ultra-shallow source/drain junctions with a parasitic series resistance limited to a small fraction of the channel ‘on’ resistance (1). With continued scaling of CMOS devices, the contact resistance will emerge as a dominant component of the junction series resistance. For conventional implanted junctions with silicide contacts, it is well established that the lowest possible contact resistivity is about , which is an order of magnitude higher than the desired contact resistivity for future MOSFETs. This fundamental limitation is set by two factors. First, the metal/semiconductor barrier height is largely determined by pinning of the silicide Fermi level near the silicon midgap. This yields a barrier height of ∼ 0.6 e V regardless of the metal used. Second. the maximum boron activation level in Si is limited to cm?3 determined by the solid solubility.