Abstract:
In NMOS transistors with boron-doped channels, Oxdation-Enhanced Diffusion (OED) is a key contributor to boron profile broadening. Starting with the arguments presented i...Show MoreMetadata
Abstract:
In NMOS transistors with boron-doped channels, Oxdation-Enhanced Diffusion (OED) is a key contributor to boron profile broadening. Starting with the arguments presented in several recent reports on the role of carbon in silicon as a sink for self-interstitials, we have explored the feasibility of using carbon in the Metal Oxide Silicon Field Effect Transistor (MOSFET) active region to retard boron diffusion during gate oxidation. A highly effective suppression of OED of boron was observed providing more than an order of magnitude reduction in boron diffusivity. MOSFETs with carbon- and boron-implanted channels have been fabricated to evaluate the impact of carbon on the electrical properties of Si. Boron diffusion, activation, and critical electrical parameters including subthreshold swing, threshold voltage, off-state leakage current, and channel mobility have been evaluated as a function of the carbon dose. While our results show that carbon can effectively suppress boron diffusion daring gate oxidation, carbon can also lead to poor boron activation and degradation in MOSFET performance when carbon dose levels above a threshold of /spl sim/10/sup 14/ cm/sup -2/ are utilized. Our results, however, indicate considerable improvement in boron activation with increases in the thermal budget. We show that if carbon implantation damage is annealed out prior to boron implantation, not only is boron activation improved, but carbon continues to serve as a sink for self-interstitials, thereby effectively suppressing OED.
Published in: IEEE Transactions on Electron Devices ( Volume: 44, Issue: 9, September 1997)
DOI: 10.1109/16.622613
Citations are not available for this document.
Cites in Patents (10)Patent Links Provided by 1790 Analytics
1.
Brodsky, MaryJane; Cai, Ming; Guo, Dechao; Henson, William K.; Narasimha, Shreesh; Liang, Yue; Song, Liyang; Wang, Yanfeng; Yeh, Chun-Chen, "Threshold voltage adjustment for thin body MOSFETs"
Inventors:
Brodsky, MaryJane; Cai, Ming; Guo, Dechao; Henson, William K.; Narasimha, Shreesh; Liang, Yue; Song, Liyang; Wang, Yanfeng; Yeh, Chun-Chen
Abstract:
A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.
Assignee:
INTERNATIONAL BUSINESS MACHINES CORP
Filing Date:
27 October 2011
Grant Date:
26 May 2015
Patent Classes:
Current U.S. Class:
438525000, 438510000, 438527000, 257365000, 257347000
Current International Class:
H01L0214250000, H01L0296600000
2.
Chidambarrao, Dureseti; Greene, Brian J.; Liang, Yue; Yu, Xiaojun, "MOS having a sic/sige alloy stack"
Inventors:
Chidambarrao, Dureseti; Greene, Brian J.; Liang, Yue; Yu, Xiaojun
Abstract:
A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.
Assignee:
INTERNATIONAL BUSINESS MACHINES CORP
Filing Date:
13 June 2013
Grant Date:
16 September 2014
Patent Classes:
Current U.S. Class:
438153000, 438142000
Current International Class:
H01L0218238000, H01L0271200000, H01L0218400000, H01L0296600000, H01L0291000000
3.
Chidambarrao, Dureseti; Greene, Brian J.; Liang, Yue; Yu, Xiaojun, "CMOS having a SiC/SiGe alloy stack"
Inventors:
Chidambarrao, Dureseti; Greene, Brian J.; Liang, Yue; Yu, Xiaojun
Abstract:
A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.
Assignee:
INTERNATIONAL BUSINESS MACHINES CORP
Filing Date:
04 January 2012
Grant Date:
02 July 2013
Patent Classes:
Current U.S. Class:
257338000, 257351000, 257369000, 257371000, 257E27064, 257E27067, 257E27108
Current International Class:
H01L0297600000, H01L0299400000, H01L0310620000, H01L0311130000, H01L0311190000, H01L0270100000, H01L0271200000, H01L0310392000
4.
Babcock, Jeffrey A.; Pinto, Angelo; Schiekofer, Manfred; Balster, Scott G.; Howard, Gregory E.; Hausler, Alfred, "CONTROL OF DOPANT DIFFUSION FROM BURIED LAYERS IN BIPOLAR INTEGRATED CIRCUITS"
Inventors:
Babcock, Jeffrey A.; Pinto, Angelo; Schiekofer, Manfred; Balster, Scott G.; Howard, Gregory E.; Hausler, Alfred
Abstract:
An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors ( 30, 50, 60 ), each having a buried collector region ( 26 '). A carbon-bearing diffusion barrier ( 28 c ) is disposed over the buried collector region ( 26 '), to inhibit the diffusion of dopant from the buried collector region ( 26 ') into the overlying epitaxial layer ( 28 ). The diffusion barrier ( 28 c ) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer ( 28 ), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks ( 52, 62 ) may be used to define the locations of the buried collector regions ( 26 ') that are to receive the carbon; for example, portions underlying eventual collector contacts ( 33, 44 c ) may be masked from the carbon implant so that dopant from the buried collector region ( 26 ') can diffuse upward to meet the contact ( 33 ). MOS transistors ( 70, 80 ) including the diffusion barrier ( 28 ) are also disclosed.
Assignee:
TEXAS INSTRUMENTS INC
Filing Date:
30 November 2009
Grant Date:
21 August 2012
Patent Classes:
Current U.S. Class:
438309000, 257E27055, 438313000, 438322000, 438340000
Current International Class:
H01L0218222
5.
Noda, Taiji, "SEMICONDUCTOR DEVICE WITH CARBON CONTAINING REGION"
Inventors:
Noda, Taiji
Abstract:
The semiconductor device of the present invention includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; and a channel doped layer of the first conductivity type formed in the semiconductor region beneath the gate electrode. The channel doped layer contains carbon as an impurity.
Assignee:
PANASONIC CORP
Filing Date:
03 March 2010
Grant Date:
07 February 2012
Patent Classes:
Current U.S. Class:
257607000, 257327000, 257335000, 257336000, 257344000, 257408000, 257655000, 257E21056, 257E21057, 257E21059, 257E21443, 257E29005, 257E29053, 257E29105, 257E29109
Current International Class:
H01L0210200
6.
Luo, Zhijiong; Liu, Yaocheng, "SEMICONDUCTOR STRUCTURE INCLUDING DOPED SILICON CARBON LINER LAYER AND METHOD FOR FABRICATION THEREOF"
Inventors:
Luo, Zhijiong; Liu, Yaocheng
Abstract:
A semiconductor structure and related method for fabrication thereof includes a liner layer interposed between: (1) a pedestal shaped channel region within a semiconductor substrate; and (2) a source region and a drain region within a semiconductor material layer located upon the liner layer and further laterally separated from the pedestal shaped channel region within the semiconductor substrate. The liner layer comprises an active doped silicon carbon material. The semiconductor material layer may comprises a semiconductor material other than a silicon carbon semiconductor material. The semiconductor material layer may alternatively comprise a silicon carbon semiconductor material having an opposite dopant polarity and lower carbon content in comparison with the liner layer. Due to presence of the silicon carbon material, the liner layer inhibits dopant diffusion therefrom into the pedestal shaped channel region. Electrical performance of a field effect device that uses the pedestal shaped channel region is thus enhanced.
Assignee:
INTERNATIONAL BUSINESS MACHINES CORP
Filing Date:
07 February 2007
Grant Date:
23 February 2010
Patent Classes:
Current U.S. Class:
257327000, 257288000, 257374000, 438303000
Current International Class:
H01L0213360
7.
Momiyama, Youichi; Okabe, Kenichi; Saiki, Takashi; Fukutome, Hidenobu, "METHOD OF SUPPRESSING DIFFUSION IN A SEMICONDUCTOR DEVICE"
Inventors:
Momiyama, Youichi; Okabe, Kenichi; Saiki, Takashi; Fukutome, Hidenobu
Abstract:
An impurity-diffused layer having an extension structure is formed first by implanting Sb ion as an impurity for forming a pocket region; then by implanting N as a diffusion-suppressive substance so as to produce two peaks in the vicinity of the interface with a gate electrode and at an amorphous/crystal interface which serves as an defect interface generated by the impurity in the pocket region; and by carrying out ion implantations for forming an extension region and deep source and drain regions.
Assignee:
FUJITSU MICROELECTRONICS LTD
Filing Date:
28 October 2005
Grant Date:
22 September 2009
Patent Classes:
Current U.S. Class:
438528000, 257E21343
Current International Class:
H01L0214250
8.
Coolbaugh, Douglas D.; Schonenberg, Kathryn T., "C IMPLANTS FOR IMPROVED SIGE BIPOLAR YIELD"
Inventors:
Coolbaugh, Douglas D.; Schonenberg, Kathryn T.
Abstract:
A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.
Assignee:
INTERNATIONAL BUSINESS MACHINES CORP
Filing Date:
11 June 2001
Grant Date:
18 March 2003
Patent Classes:
Current U.S. Class:
438312000, 257197000, 257E21335, 257E21371, 257E29046, 257E29193, 438528000
Current International Class:
H01L0213310000
9.
Gossmann, Hans-Joachim Ludwig; Rafferty, Conor Stefan, "PROCESS FOR CONTROLLING DOPANT DIFFUSION IN A SEMICONDUCTOR LAYER AND SEMICONDUCTOR DEVICE FORMED THEREBY"
Inventors:
Gossmann, Hans-Joachim Ludwig; Rafferty, Conor Stefan
Abstract:
A semiconductor device having a carbon-containing region with an advantageous concentration profile is disclosed. The carbon is introduced into a region of the substrate and at a depth below the space-charge layer of the device and at a concentration such that the carbon atoms absorb point defects created in the substrate during device fabrication but do not adversely affect the leakage characteristics of the device.
Assignee:
LUCENT TECHNOLOGIES INC
Filing Date:
30 January 1998
Grant Date:
28 November 2000
Patent Classes:
Current U.S. Class:
257607000, 257065000, 257066000, 257610000, 257611000, 257612000, 257652000, 257E21111, 257E21135, 257E21341, 257E29040, 257E29062, 257E29086, 257E29297
Current International Class:
H01L0291670000
10.
Kodama, Noriyuki, "METHOD FOR FABRICATING A FIELD EFFECT TRANSISTOR HAVING ELEVATED SOURCE DRAIN REGIONS"
Inventors:
Kodama, Noriyuki
Abstract:
A method of making a semiconductor device with a shallow (on the order of 50 nm) PN junction depth includes the steps of forming, on a region of a semiconductor substrate in which an impurity diffusion region having the shallow PN junction depth is to be formed, a selectively grown silicon layer (raised layer) containing a substance such as carbon which easily combines with point defects in the semiconductor substrate or a substance such as nitrogen which prevents an impurity providing an electrical conductivity from diffusing, ion-implanting an impurity of one conductivity type into the selectively grown silicon layer, and forming the diffusion region by activating the implanted impurity of one conductivity type and diffusing the impurity of one conductivity type into the semiconductor substrate, by means of heat treatment.
Assignee:
NEC CORP
Filing Date:
30 July 1997
Grant Date:
19 October 1999
Patent Classes:
Current U.S. Class:
438300000, 257E21054, 257E21102, 257E21151, 257E21430, 257E21438, 257E29040, 257E29086, 438301000
Current International Class:
H01L0213360000
