Abstract:
Bandgap-engineered W/Si/sub 1-x/Ge/sub x//Si junctions (p/sup +/ and n/sup +/) with ultra-low contact resistivity and low leakage have been fabricated and characterized. ...Show MoreMetadata
Abstract:
Bandgap-engineered W/Si/sub 1-x/Ge/sub x//Si junctions (p/sup +/ and n/sup +/) with ultra-low contact resistivity and low leakage have been fabricated and characterized. The junctions are formed via outdiffusion from a selectively deposited Si/sub 0.7/Ge/sub 0.3/ layer which is implanted and annealed using RTA. The Si/sub 1-x/Ge/sub x/ layer can then be selectively thinned using NH/sub 4/OH/H/sub 2/O/sub 2//H/sub 2/O at 75/spl deg/C with little change in characteristics or left as-deposited. Leakage currents were better than 1.6/spl times/10/sup -9/ A/cm/sup 2/ (areal), 7.45/spl times/10/sup -12/ A/cm (peripheral) for p/sup +//n and 3.5/spl times/10/sup -10/ A/cm/sup 2/ (peripheral) for n/sup +//p. W contacts were formed using selective LPCVD on Si/sub 1-x/Ge/sub x/. A specific contact resistivity of better than 3.2/spl times/10/sup -8/ /spl Omega/ cm/sup 2/ for p/sup +//n and 2.2/spl times/10/sup -8/ /spl Omega/ cm/sup 2/ for n/sup +//p is demonstrated-an order of magnitude n/sup +/ better than current TiSi/sub 2/ technology. W/Si/sub 1-x/Ge/sub x//Si junctions show great potential for ULSI applications.
Published in: IEEE Electron Device Letters ( Volume: 17, Issue: 7, July 1996)
DOI: 10.1109/55.506367
Citations are not available for this document.
Cites in Patents (7)Patent Links Provided by 1790 Analytics
1.
Fitzgerald, Eugene A., "Methods of fabricating contact regions for FET incorporating SiGe"
Inventors:
Fitzgerald, Eugene A.
Abstract:
Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
Filing Date:
26 May 2004
Grant Date:
02 September 2014
Patent Classes:
Current U.S. Class:
438197000, 438285000, 438286000, 438763000, 438E21129
Current International Class:
H01L0297200000
2.
Currie, Matthew T.; Hammond, Richard, "REACTED CONDUCTIVE GATE ELECTRODES"
Inventors:
Currie, Matthew T.; Hammond, Richard
Abstract:
A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
Filing Date:
17 September 2004
Grant Date:
06 March 2012
Patent Classes:
Current U.S. Class:
257616000, 257E21164
Current International Class:
H01L0311170
3.
Lochtefeld, Anthony J.; Langdo, Thomas A.; Westhoff, Richard, "ELEVATED SOURCE AND DRAIN ELEMENTS FOR STRAINED CHANNEL HETEROJUNTION FIELD EFFECT TRANSISTORS"
Inventors:
Lochtefeld, Anthony J.; Langdo, Thomas A.; Westhoff, Richard
Abstract:
A semiconductor structure having a surface layer disposed over a substrate, the surface layer including strained silicon. A contact layer is disposed over a portion of the surface layer, the contact layer including a metal-semiconductor alloy. A bottommost boundary of the contact layer is disposed above a bottommost boundary of the surface layer.
Assignee:
AMBERWAVE SYSTEMS CORP
Filing Date:
07 June 2002
Grant Date:
10 November 2009
Patent Classes:
Current U.S. Class:
257377000, 257384000, 257E29268
Current International Class:
H01L0270880, H01L0294500
4.
Fitzgerald, Eugene A., "RELAXED SIGE PLATFORM FOR HIGH SPEED CMOS ELECTRONICS AND HIGH SPEED ANALOG CIRCUITS"
Inventors:
Fitzgerald, Eugene A.
Abstract:
Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
Assignee:
AMBERWAVE SYSTEMS CORP
Filing Date:
09 February 2004
Grant Date:
10 March 2009
Patent Classes:
Current U.S. Class:
438763000, 438719000, 438762000
Current International Class:
H01L0213100
5.
Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., "STRAINED SEMICONDUCTOR ON INSULATOR DEVICE STRUCTURES WITH ELEVATED SOURCE DRAIN REGIONS"
Inventors:
Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A.
Abstract:
The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
Assignee:
AMBERWAVE SYSTEMS CORP
Filing Date:
10 May 2005
Grant Date:
02 September 2008
Patent Classes:
Current U.S. Class:
257018000, 257192000, 257E21121, 257E21127, 257E21129, 257E21371, 257E21415, 257E21442, 257E21448, 257E21564, 257E21568, 257E21570, 257E21703, 257E27112, 257E29295, 257E29297, 257E29298
Current International Class:
H01L0213360
6.
Currie, Matthew T.; Hammond, Richard, "METHODS OF FORMING REACTED CONDUCTIVE GATE ELECTRODES"
Inventors:
Currie, Matthew T.; Hammond, Richard
Abstract:
A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
Assignee:
AMBERWAVE SYSTEMS CORP
Filing Date:
07 March 2005
Grant Date:
15 May 2007
Patent Classes:
Current U.S. Class:
438149000, 257E21165, 257E21201, 257E21207, 257E21438, 257E29056, 438157000
Current International Class:
H01L0210000
7.
Langdo, Thomas A.; Lochtefeld, Anthony J., "METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES HAVING EPITAXIALLY GROWN SOURCE AND DRAIN ELEMENTS"
Inventors:
Langdo, Thomas A.; Lochtefeld, Anthony J.
Abstract:
Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on the semiconductor substrate while in situ doping the epitaxial layer to suppress facet formation. Suppression of faceting during selective epitaxial growth by in situ doping of the epitaxial layer at a predetermined level rather than by manipulating spacer composition and geometry alleviates the stringent requirements on the device design and increases tolerance to variability during the spacer fabrication.
Assignee:
AMBERWAVE SYSTEMS CORP
Filing Date:
10 June 2003
Grant Date:
20 September 2005
Patent Classes:
Current U.S. Class:
438481000, 257E21131, 257E21171, 257E21430, 257E21438, 257E29056, 257E29146, 257E29267, 438504000
Current International Class:
H01L0212000000
