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Ke Zheng - IEEE Xplore Author Profile

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Author details

Ke Zheng

Publications

28

Citations

738

Publications by Year

20182025

Co-Authors:

Aitor Alvarez-GilaBoaz AradOhad Ben-ShaharYigit Baran CanJocelyn Chanussot

Show All Co-Authors (88)

Ke Zheng

Affiliation

College of Geography and Environment

Liaocheng University

Liaocheng, China

Publication Topics

Multispectral Images,
Peak Signal-to-noise Ratio,
Spectral Angle Mapper,
Spectral Response Function,
Convolutional Layers,
Convolutional Neural Network,
Point Spread Function,
High-resolution Multispectral Image,
Spatial Resolution,
Deep Learning,
Fusion Results,
Hyperspectral Image Super-resolution

Biography

Ke Zheng received the B.S. degree in geographic information system from Shandong Agricultural University, Taian, China, in 2008, and the M.S. and Ph.D. degrees in remote sensing from the College of Geosciences and Surveying Engineering, China University of Mining and Technology (Beijing), Beijing, China, in 2016 and 2020, respectively.,Since 2020, he has been a Post-Doctoral Associate with the Key Laboratory of Digital Earth Science, Aerospace Information Research Institute, Chinese Academy of Science, Beijing. His research interests include image processing, machine learning, deep learning and their application in Earth Vision.(Based on document published on 15 July 2020).

Publications

28

Citations

738

Publications by Year

20182025

Co-Authors:

Aitor Alvarez-Gila
Boaz Arad
Ohad Ben-Shahar
Yigit Baran Can
Jocelyn Chanussot

Show All Co-Authors (88)

Author's Published Works

Search History

Showing 1-15 of 15 results

Conferences (13)

Journals (2)

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Single Year
H. Kimijima(15)
T. Ohguro(14)
H. Iwai(14)
E. Morifuji(14)
Y. Katsumata(14)
Toshiba Corporation, Kawasaki, Japan(5)
Microelectronics Engineering Laboratory, Toshiba Corporation, Yokohama, Japan(3)
Microelectronics Engineering Laboratory, Toshiba Corporation, Kawasaki, Japan(3)
Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP(2)
Multimedia Engineering Laboratory, Toshiba Corporation, Japan(1)
International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)(4)
1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)(3)
1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)(2)
IEEE Transactions on Electron Devices(2)
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)(1)
IEEE(15)
San Francisco, CA, USA(5)
Honolulu, HI, USA(3)
Kyoto, Japan(3)
Leuven, Belgium(1)
Washington, DC, USA(1)
Gate Length(9)
Gate Oxide(7)
Gate Electrode(6)
polySia(5)
Drain Current(4)

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Results

A low power 40nm CMOS technology featuring extremely high density of logic (2100kGate/mm2) and SRAM (0.195μm2) for wide range of mobile applications with wireless system

R. Watanabe;A. Oishi;T. Sanuki;H. Kimijima;K. Okamoto;S. Fujita;H. Fukui;K. Yoshida;H. Otani;E. Morifuji;K. Kojima;M. Inohara;H. Igrashi;K. Honda;H. Yoshimura;T. Nakayama;S. Miyake;T. Hirai;T. Iwamoto;Y. Nakahara;K. Kinoshita;T. Morimoto;S. Kobayashi;S. Kyoh;M. Ikeda;K. Imai;M. Iwai;N. Nakamura;F. Matsuoka

2008 IEEE International Electron Devices Meeting

Year: 2008 | Conference Paper |

Cited by: Papers (3) | Patents (3)

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Extremely high density CMOS technology for 40nm low power applications is demonstrated. More than 50% power reduction is achieved as a SoC chip by aggressive shrinkage and low voltage operation of RF devices. Gate density of 2100kGate/mm2 is realized by breaking down conventional trade-off of leakage power and performance with three key approaches. 0.195μm2 SRAM with excellent static noise margin ...Show More

A low power 40nm CMOS technology featuring extremely high density of logic (2100kGate/mm2) and SRAM (0.195μm2) for wide range of mobile applications with wireless system

R. Watanabe;A. Oishi;T. Sanuki;H. Kimijima;K. Okamoto;S. Fujita;H. Fukui;K. Yoshida;H. Otani;E. Morifuji;K. Kojima;M. Inohara;H. Igrashi;K. Honda;H. Yoshimura;T. Nakayama;S. Miyake;T. Hirai;T. Iwamoto;Y. Nakahara;K. Kinoshita;T. Morimoto;S. Kobayashi;S. Kyoh;M. Ikeda;K. Imai;M. Iwai;N. Nakamura;F. Matsuoka

2008 IEEE International Electron Devices Meeting

Year: 2008 | Conference Paper |

RF modelling for 0.1um gate length MOSFETs

E. Morifuji;T. Ohguro;H. Kimijima;T. Yoshitomi;H.S. Momose;Y. Katsumata;K. Ishimaru;F. Matsuoka;M. Kinugawa;H. Iwai

29th European Solid-State Device Research Conference

Year: 1999 | Conference Paper |

Cited by: Papers (1)

First Page of the Article

RF modelling for 0.1um gate length MOSFETs

E. Morifuji;T. Ohguro;H. Kimijima;T. Yoshitomi;H.S. Momose;Y. Katsumata;K. Ishimaru;F. Matsuoka;M. Kinugawa;H. Iwai

29th European Solid-State Device Research Conference

Year: 1999 | Volume: 1 | Conference Paper |

Improvement of direct-tunneling gate leakage current in ultra-thin gate oxide CMOS with TiN gate electrode using non-doped selective epitaxial Si channel technique

H.S. Momose;T. Ohguro;E. Morifuji;H. Sugaya;S. Nakamura;T. Yoshitomi;H. Kimijima;T. Morimoto;F. Matsuoka;Y. Katsumata;H. Ishiuchi;H. Iwai

International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)

Year: 1999 | Conference Paper |

Cited by: Patents (2)

A non-doped selective epitaxial Si channel technique has been applied to ultra-thin gate oxide CMOS transistors with TiN and polysilicon gate electrodes, and its effect on direct-tunneling gate leakage current has been investigated. It was found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current in both the TiN and polysilicon gate electrode cases. Improved ...Show More

Improvement of direct-tunneling gate leakage current in ultra-thin gate oxide CMOS with TiN gate electrode using non-doped selective epitaxial Si channel technique

H.S. Momose;T. Ohguro;E. Morifuji;H. Sugaya;S. Nakamura;T. Yoshitomi;H. Kimijima;T. Morimoto;F. Matsuoka;Y. Katsumata;H. Ishiuchi;H. Iwai

International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)

Year: 1999 | Conference Paper |

Improvement of 1/f noise by using VHP (vertical high pressure) oxynitride gate insulator for deep-sub micron RF and analog CMOS

H. Kimijima;T. Ohguro;B. Evans;B. Acker;J. Bloom;H. Mabuchi;Dim-Lee Kwong;E. Morifuji;T. Yoshitomi;H.S. Momose;M. Kinugawa;Y. Katsumata;H. Iwai

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)

Year: 1999 | Conference Paper |

Cited by: Papers (8) | Patents (3)

The 1/f noise in MOSFETs using VHP (vertical high pressure) oxynitride gate insulator was studied. The 1/f noise is degraded by conventional oxynitride gate insulators. It was found that 1/f noise can be improved by using the VHP oxynitride gate insulator.Show More

Improvement of 1/f noise by using VHP (vertical high pressure) oxynitride gate insulator for deep-sub micron RF and analog CMOS

H. Kimijima;T. Ohguro;B. Evans;B. Acker;J. Bloom;H. Mabuchi;Dim-Lee Kwong;E. Morifuji;T. Yoshitomi;H.S. Momose;M. Kinugawa;Y. Katsumata;H. Iwai

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)

Year: 1999 | Conference Paper |

Future perspective and scaling down roadmap for RF CMOS

E. Morifuji;H.S. Momose;T. Ohguro;T. Yoshitomi;H. Kimijima;F. Matsuoka;M. Kinugawa;Y. Katsumata;H. Iwai

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)

Year: 1999 | Conference Paper |

Cited by: Papers (41)

The concept of future scaling-down for RF CMOS technology has been investigated in terms of f/sub T/, f/sub max/, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are key parameters, especially in sub-100 nm gate length generations.Show More

Future perspective and scaling down roadmap for RF CMOS

E. Morifuji;H.S. Momose;T. Ohguro;T. Yoshitomi;H. Kimijima;F. Matsuoka;M. Kinugawa;Y. Katsumata;H. Iwai

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)

Year: 1999 | Conference Paper |

Future perspective and scaling down roadmap for RF CMOS

E. Morifuji;H.S. Momose;T. Ohguro;T. Yoshitomi;H. Kimijima;F. Matsuoka;M. Kinugawa;Y. Katsumata;H. Iwai

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

Year: 1999 | Conference Paper |

Cited by: Papers (25)

Concept of future scaling-down for RF CMOS has been investigated in terms of fT, fmax, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are the key parameters especially in sub-100 nm gate length generations.Show More

Future perspective and scaling down roadmap for RF CMOS

E. Morifuji;H.S. Momose;T. Ohguro;T. Yoshitomi;H. Kimijima;F. Matsuoka;M. Kinugawa;Y. Katsumata;H. Iwai

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

Year: 1999 | Conference Paper |

An 0.18-/spl mu/m CMOS for mixed digital and analog applications with zero-volt-V/sub th/ epitaxial-channel MOSFETs

T. Ohguro;H. Naruse;H. Sugaya;E. Morifuji;S. Nakamura;T. Yoshitomi;T. Morimoto;H. Kimijima;H. Sasaki Momose;Y. Katsumata;H. Iwai

IEEE Transactions on Electron Devices

Year: 1999 | Volume: 46, Issue: 7 | Journal Article |

Cited by: Papers (10) | Patents (105)

An 0.18-/spl mu/m CMOS technology with multi-V/sub th/s for mixed high-speed digital and RF-analog applications has been developed. The V/sub th/s of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFET's with zero-volt-V/sub th/ for RF analog circuits. The zero-volt-V/sub th/ MOSFETs were made by using undoped epitaxial layer for the c...Show More

An 0.18-/spl mu/m CMOS for mixed digital and analog applications with zero-volt-V/sub th/ epitaxial-channel MOSFETs

T. Ohguro;H. Naruse;H. Sugaya;E. Morifuji;S. Nakamura;T. Yoshitomi;T. Morimoto;H. Kimijima;H. Sasaki Momose;Y. Katsumata;H. Iwai

IEEE Transactions on Electron Devices

Year: 1999 | Volume: 46, Issue: 7 | Journal Article |

A study of flicker noise in n- and p-MOSFETs with ultra-thin gate oxide in the direct-tunneling regime

H.S. Momose;H. Kimijima;S. Ishizuka;Y. Miyahara;T. Ohguro;T. Yoshitomi;E. Morifuji;S. Nakamura;T. Morimoto;Y. Katsumata;H. Iwai

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)

Year: 1998 | Conference Paper |

Cited by: Papers (14) | Patents (1)

Flicker noise characteristics of 1.5 nn direct-tunneling gate oxide n- and pMOSFETs have been investigated It was confirmed that in the shorter gate length region, less than 0.2 /spl mu/m, the flicker noise decreased with the decrease in gate oxide thickness even in the direct-tunneling regime. On the contrary, it was found that with gate length larger than 0.45 /spl mu/m, the flicker noise become...Show More

A study of flicker noise in n- and p-MOSFETs with ultra-thin gate oxide in the direct-tunneling regime

H.S. Momose;H. Kimijima;S. Ishizuka;Y. Miyahara;T. Ohguro;T. Yoshitomi;E. Morifuji;S. Nakamura;T. Morimoto;Y. Katsumata;H. Iwai

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)

Year: 1998 | Conference Paper |

A study of self-align doped channel structure for low power and low l/f noise operation

A. Yoshitomi;H. Kimijima;S. Ishizuka;Y. Miyahara;T. Ohguro;E. Morifuji;T. Morimoto;H.S. Momose;Y. Katsumata;H. Iwai

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

Year: 1998 | Conference Paper |

Cited by: Papers (2)

For low power operation in analog CMOS, a lot of attempts using new drain structures to reduce the parasitic capacitance of the source and drain junction capacitance (Cj) have been reported. However, there are not many approaches from the channel doping process. In the usual MOSFET structures, the highly doped channel implanted regions are localized under the gate by the mask used in the channel i...Show More

A study of self-align doped channel structure for low power and low l/f noise operation

A. Yoshitomi;H. Kimijima;S. Ishizuka;Y. Miyahara;T. Ohguro;E. Morifuji;T. Morimoto;H.S. Momose;Y. Katsumata;H. Iwai

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

Year: 1998 | Conference Paper |

Process induced damage on RFCMOS

E. Morifuji;T. Ohguro;T. Yoshitomi;H. Kimijima;T. Morimoto;H.S. Momose;Y. Katsumata;H. Iwai

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)

Year: 1998 | Conference Paper |

Cited by: Papers (1)

We have investigated the correlation between process induced damage and RF analog characteristics. Vth matching, fmax, and NFmin were analyzed using mass data. It was found that the redistribution of channel profile due to the damage induced by ion implantation at the gate edge affects the spread of fmax and NFmin. This tendency was not apparent in the spread of fT.Show More

Process induced damage on RFCMOS

E. Morifuji;T. Ohguro;T. Yoshitomi;H. Kimijima;T. Morimoto;H.S. Momose;Y. Katsumata;H. Iwai

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)

Year: 1998 | Conference Paper |

0.12 /spl mu/m raised gate/source/drain epitaxial channel NMOS technology

T. Ohguro;H. Naruse;H. Sugaya;H. Kimijima;E. Morifuji;T. Yoshitomi;T. Morimoto;H.S. Momose;Y. Katsumata;H. Iwai

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)

Year: 1998 | Conference Paper |

Cited by: Papers (11)

We introduce a 0.12 /spl mu/m nMOS technology with multi-Vth's for mixed high-speed digital and RF-analog applications. Though basically device parameter was determined by SIA roadmap, new structures such as undoped epitaxial channel and raised gate/source/drain were applied to a 0.12 /spl mu/m nMOS. This device has high fT and low noise figure which are very important for RF analog circuit design...Show More

0.12 /spl mu/m raised gate/source/drain epitaxial channel NMOS technology

T. Ohguro;H. Naruse;H. Sugaya;H. Kimijima;E. Morifuji;T. Yoshitomi;T. Morimoto;H.S. Momose;Y. Katsumata;H. Iwai

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)

Year: 1998 | Conference Paper |

On-chip spiral inductors with diffused shields using channel-stop implant

T. Yoshitomi;Y. Sugawara;E. Morifuji;T. Ohguro;H. Kimijima;T. Morimoto;H.S. Momose;Y. Katsumata;H. Iwai

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)

Year: 1998 | Conference Paper |

Cited by: Papers (9) | Patents (4)

We investigated the Diffused shield Under the Oxide (DUO) for the first time. DUO is an extremely shallow diffusion layer in the n-well under the field oxide. DUO can be formed by high energy implantation through the field oxide, and it can be formed by the process of the channel stop implant for MOSFETs simultaneously. Application of DUO provided a 79% improvement in Q-factor and the comparable s...Show More

On-chip spiral inductors with diffused shields using channel-stop implant

T. Yoshitomi;Y. Sugawara;E. Morifuji;T. Ohguro;H. Kimijima;T. Morimoto;H.S. Momose;Y. Katsumata;H. Iwai

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)

Year: 1998 | Conference Paper |

RF noise in 1.5 nm gate oxide MOSFETs and the evaluation of the NMOS LNA circuit integrated on a chip

H.S. Momose;R. Fujimoto;S. Otaka;E. Morifuji;T. Ohguro;T. Yoshitomi;H. Kimijima;S. Nakamura;T. Morimoto;Y. Katsumata;H. Tanimoto;H. Iwai

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

Year: 1998 | Conference Paper |

Cited by: Papers (13)

Recently, direct tunneling gate oxide MOSFETs have shown the potential of enabling extremely high RF performance in analog applications. An excellent cutoff frequency of more than 150 GHz was reported at a gate length of less than 0.1 /spl mu/m. In this paper, RF noise characteristics of the MOSFETs are reported in detail. The gate oxide thickness and supply voltage dependencies were investigated....Show More

RF noise in 1.5 nm gate oxide MOSFETs and the evaluation of the NMOS LNA circuit integrated on a chip

H.S. Momose;R. Fujimoto;S. Otaka;E. Morifuji;T. Ohguro;T. Yoshitomi;H. Kimijima;S. Nakamura;T. Morimoto;Y. Katsumata;H. Tanimoto;H. Iwai

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

Year: 1998 | Conference Paper |

High performance RF characteristics of raised gate/source/drain CMOS with Co salicide

T. Ohguro;H. Naruse;H. Sugaya;S. Nakamura;E. Morifuji;H. Kimijima;T. Yoshitomi;T. Morimoto;H.S. Momose;Y. Katsumata;H. Iwai

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

Year: 1998 | Conference Paper |

Cited by: Papers (19) | Patents (28)

In order to obtain high performance analog MOSFETs, it is important to reduce gate resistance. Recently W/Ti, CoSi/sub 2/ and NiSi gate electrodes have been proposed to realize these requirements. Especially, the Co salicided T-shape gate electrode realizes easily a low gate resistance below 1.5 ohm/sq. with a small increase in the number of process steps. Additionally, short channel effects are i...Show More

High performance RF characteristics of raised gate/source/drain CMOS with Co salicide

T. Ohguro;H. Naruse;H. Sugaya;S. Nakamura;E. Morifuji;H. Kimijima;T. Yoshitomi;T. Morimoto;H.S. Momose;Y. Katsumata;H. Iwai

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

Year: 1998 | Conference Paper |

Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD with preheating

T. Ohguro;N. Sugiyama;S. Imai;K. Usuda;M. Saito;T. Yoshitomi;M. Ono;H. Kimijima;H.S. Momose;Y. Katsumata;H. Iwai

IEEE Transactions on Electron Devices

Year: 1998 | Volume: 45, Issue: 3 | Journal Article |

Cited by: Papers (25) | Patents (11)

Undoped epitaxial channel n-MOSFET with high transconductance was developed. In order to obtain a good crystal quality of the epitaxial layer and, thus, to achieve high performance, it is important to reduce the oxygen concentration at the epitaxial Si/Si substrate interface. In this paper, we describe the relationship between the electrical characteristics and the surface density of oxygen at the...Show More

Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD with preheating

T. Ohguro;N. Sugiyama;S. Imai;K. Usuda;M. Saito;T. Yoshitomi;M. Ono;H. Kimijima;H.S. Momose;Y. Katsumata;H. Iwai

IEEE Transactions on Electron Devices

Year: 1998 | Volume: 45, Issue: 3 | Journal Article |

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