Abstract:
An 0.18-/spl mu/m CMOS technology with multi-V/sub th/s for mixed high-speed digital and RF-analog applications has been developed. The V/sub th/s of MOSFETs for digital ...Show MoreMetadata
Abstract:
An 0.18-/spl mu/m CMOS technology with multi-V/sub th/s for mixed high-speed digital and RF-analog applications has been developed. The V/sub th/s of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFET's with zero-volt-V/sub th/ for RF analog circuits. The zero-volt-V/sub th/ MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD) at 750/spl deg/C, the film quality is as good as the bulk silicon because high pre-heating temperature (940/spl deg/C for 30 s) is used in H/sub 2/ atmosphere before the epitaxial growth. The epitaxial channel MOSFET shows higher peak g/sub m/ and f/sub T/ values than those of bulk cases. Furthermore, the g/sub m/ and f/sub T/ values of the epitaxial channel MOSFET show significantly improved performances under the lower supply voltage compared with those of bulk. This is very important for RF analog application for low supply voltage. The undoped-epitaxial-channel MOSFETs with zero-V/sub th/ will become a key to realize high-performance and low-power CMOS devices for mixed digital and RF-analog applications.
Published in: IEEE Transactions on Electron Devices ( Volume: 46, Issue: 7, July 1999)
DOI: 10.1109/16.772479
Citations are not available for this document.
Cites in Patents (105)Patent Links Provided by 1790 Analytics
1.
Thompson, Scott E.; Thummalapally, Damodar R., "Electronic devices and systems, and methods for making and using the same"
Inventors:
Thompson, Scott E.; Thummalapally, Damodar R.
Abstract:
Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sV(sub)T compared to conventional bulk CMOS and can allow the threshold voltage V(sub)T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
Assignee:
UNITED SEMICONDUCTOR JAPAN CO LTD
Filing Date:
12 September 2018
Grant Date:
13 July 2021
Patent Classes:
Current International Class:
H01L0218234000, H01L0218238000, H01L0218400000, H01L0270200000, H01L0271100000, H01L0291000000, H01L0296600000, H01L0297800000, H01L0212650000, H01L0210200000, H01L0270920000, H01L0290600000
2.
Kidd, David A., "Tipless transistors, short-tip transistors, and methods and circuits therefor"
Inventors:
Kidd, David A.
Abstract:
An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
27 March 2018
Grant Date:
25 February 2020
Patent Classes:
Current International Class:
H01L0270880000, H03K0176870000, H01L0293600000, H01L0294230000, H01L0297800000, H03K0033560000, H03K0050600000, H03L0070800000, G11C0070800000, H01L0291000000, G11C0070600000, H03L0070810000
3.
Shifren, Lucian; Ranade, Pushkar; Gregory, Paul E.; Sonkusale, Sachin R.; Zhang, Weimin; Thompson, Scott E., "Advanced transistors with punch through suppression"
Inventors:
Shifren, Lucian; Ranade, Pushkar; Gregory, Paul E.; Sonkusale, Sachin R.; Zhang, Weimin; Thompson, Scott E.
Abstract:
An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5¿10(sup)18 dopant atoms per cm(sup)3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
20 October 2016
Grant Date:
18 June 2019
Patent Classes:
Current International Class:
H01L0291000000, H01L0218234000, H01L0270880000, H01L0296600000, H01L0297800000, H01L0270920000, H01L0290800000, H01L0293600000
4.
Thompson, Scott E.; Clark, Lawrence T., "Digital circuits having improved transistors, and methods therefor"
Inventors:
Thompson, Scott E.; Clark, Lawrence T.
Abstract:
Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
27 April 2018
Grant Date:
02 April 2019
Patent Classes:
Current International Class:
H01L0250000000, H03K0190000000, H03K0190948000, H01L0270880000, G11C0114120000, H01L0271180000, H01L0291000000, H01L0271100000
5.
Thompson, Scott E.; Thummalapally, Damodar R., "Electronic devices and systems, and methods for making and using the same"
Inventors:
Thompson, Scott E.; Thummalapally, Damodar R.
Abstract:
Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sV(sub)T compared to conventional bulk CMOS and can allow the threshold voltage V(sub)T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
19 August 2016
Grant Date:
05 March 2019
Patent Classes:
Current International Class:
H01L0218234000, H01L0218238000, H01L0218400000, H01L0270200000, H01L0271100000, H01L0291000000, H01L0296600000, H01L0297800000, H01L0212650000, H01L0210200000, H01L0270920000, H01L0290600000
6.
Thompson, Scott E.; Thummalapally, Damodar R., "Electronic devices and systems, and methods for making and using the same"
Inventors:
Thompson, Scott E.; Thummalapally, Damodar R.
Abstract:
Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sV(sub)T compared to conventional bulk CMOS and can allow the threshold voltage V(sub)T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
04 January 2017
Grant Date:
26 February 2019
Patent Classes:
Current International Class:
H01L0218234000, H01L0218238000, H01L0218400000, H01L0270200000, H01L0271100000, H01L0291000000, H01L0296600000, H01L0297800000, H01L0212650000, H01L0210200000, H01L0270920000, H01L0290600000
7.
Zhao, Dalong; Bakhishev, Teymur; Scudder, Lance; Gregory, Paul E.; Duane, Michael; Sridharan, U. C.; Ranade, Pushkar; Shifren, Lucian; Hoffmann, Thomas, "Semiconductor structure with multiple transistors having various threshold voltages"
Inventors:
Zhao, Dalong; Bakhishev, Teymur; Scudder, Lance; Gregory, Paul E.; Duane, Michael; Sridharan, U. C.; Ranade, Pushkar; Shifren, Lucian; Hoffmann, Thomas
Abstract:
A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
26 April 2018
Grant Date:
26 February 2019
Patent Classes:
Current International Class:
H01L0296600000, H01L0270880000, H01L0291000000, H01L0218234000, H01L0212650000, H01L0212830000
8.
Thompson, Scott E.; Thummalapally, Damodar R., "Electronic devices and systems, and methods for making and using same"
Inventors:
Thompson, Scott E.; Thummalapally, Damodar R.
Abstract:
Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sigma V(sub)T compared to conventional bulk CMOS and can allow the threshold voltage V(sub)T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
09 March 2015
Grant Date:
11 September 2018
Patent Classes:
Current International Class:
H01L0218234000, H01L0210200000, H01L0212650000, H01L0218238000, H01L0271100000, H01L0291000000, H01L0296600000, H01L0297800000, H01L0218400000, H01L0270200000
9.
Zhao, Dalong; Bakhishev, Teymur; Scudder, Lance; Gregory, Paul E.; Duane, Michael; Sridharan, U. C.; Ranade, Pushkar; Shifren, Lucian; Hoffmann, Thomas, "Semiconductor structure with multiple transistors having various threshold voltages"
Inventors:
Zhao, Dalong; Bakhishev, Teymur; Scudder, Lance; Gregory, Paul E.; Duane, Michael; Sridharan, U. C.; Ranade, Pushkar; Shifren, Lucian; Hoffmann, Thomas
Abstract:
A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
18 February 2016
Grant Date:
03 July 2018
Patent Classes:
Current International Class:
H01L0296600000, H01L0270880000, H01L0291000000, H01L0218234000
10.
Bakhishev, Teymur; Wang, Lingquan; Zhao, Dalong; Ranade, Pushkar; Thompson, Scott E., "Buried channel deeply depleted channel transistor"
Inventors:
Bakhishev, Teymur; Wang, Lingquan; Zhao, Dalong; Ranade, Pushkar; Thompson, Scott E.
Abstract:
Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
25 July 2017
Grant Date:
05 June 2018
Patent Classes:
Current International Class:
H01L0297600000, H01L0299400000, H01L0310620000, H01L0311130000, H01L0311190000, H01L0271460000, H04N0053745000, H01L0297800000, H01L0291000000
11.
Thompson, Scott E.; Clark, Lawrence T., "Digital circuits having improved transistors, and methods therefor"
Inventors:
Thompson, Scott E.; Clark, Lawrence T.
Abstract:
Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
27 October 2017
Grant Date:
29 May 2018
Patent Classes:
Current International Class:
H01L0250000000, H03K0190000000, G11C0114120000, H01L0271180000, H01L0291000000
12.
Clark, Lawrence T.; Thompson, Scott E.; Roy, Richard S.; Rogenmoser, Robert; Thummalapally, Damodar R., "Integrated circuit devices and methods"
Inventors:
Clark, Lawrence T.; Thompson, Scott E.; Roy, Richard S.; Rogenmoser, Robert; Thummalapally, Damodar R.
Abstract:
An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
27 June 2017
Grant Date:
08 May 2018
Patent Classes:
Current International Class:
G11C0070000000, G11C0114180000, G11C0114190000, H01L0271100000, H01L0297800000, H01L0291000000
13.
Kidd, David A., "Tipless transistors, short-tip transistors, and methods and circuits therefor"
Inventors:
Kidd, David A.
Abstract:
An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
04 January 2017
Grant Date:
24 April 2018
Patent Classes:
Current International Class:
H01L0270880000, H01L0291000000, H01L0297800000, H03L0070800000, H03L0070810000, H03K0050600000, H03K0033560000, G11C0070800000, G11C0070600000
14.
Arghavani, Reza; Ranade, Pushkar; Shifren, Lucian; Thompson, Scott E.; de Villeneuve, Catherine, "Transistor with threshold voltage set notch and method of fabrication thereof"
Inventors:
Arghavani, Reza; Ranade, Pushkar; Shifren, Lucian; Thompson, Scott E.; de Villeneuve, Catherine
Abstract:
A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sV(sub)T (variation in V(sub)T) compared to conventional bulk CMOS and can allow the threshold voltage V(sub)T of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the V(sub)T setting within a precise range. This V(sub)T set range may be extended by appropriate selection of metals of a gate electrode material so that a very wide range of V(sub)T settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control V(sub)T (with a low sV(sub)T) and V(sub)DD (the operating voltage supplied to the transistor), so that the body bias can be tuned separately from V(sub)T for a given device.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
24 June 2016
Grant Date:
20 March 2018
Patent Classes:
Current International Class:
H01L0291000000, H01L0270920000, H01L0218234000, H01L0270880000, H01L0293600000, H01L0296600000, H01L0297800000, H01L0218238000, H01L0290600000, H01L0294900000
15.
Bakhishev, Teymur; Pradhan, Sameer; Hoffmann, Thomas; Sonkusale, Sachin R., "Method for fabricating a transistor device with a tuned dopant profile"
Inventors:
Bakhishev, Teymur; Pradhan, Sameer; Hoffmann, Thomas; Sonkusale, Sachin R.
Abstract:
A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. Different transistor devices with similar boron implants may be fabricated with different peak locations and heights for their respective dopant profiles by tailoring the carbon implant energy to effect tuned dopant profiles for the boron.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
04 October 2016
Grant Date:
13 February 2018
Patent Classes:
Current International Class:
H01L0290200000, H01L0291000000, H01L0212650000, H01L0296600000, H01L0297800000, H01L0210200000
16.
Shifren, Lucian; Ranade, Pushkar; Thompson, Scott E.; Sonkusale, Sachin R.; Zhang, Weimin, "Low power semiconductor transistor structure and method of fabrication thereof"
Inventors:
Shifren, Lucian; Ranade, Pushkar; Thompson, Scott E.; Sonkusale, Sachin R.; Zhang, Weimin
Abstract:
A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sV(sub)T compared to conventional bulk CMOS and can allow the threshold voltage V(sub)T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
21 September 2016
Grant Date:
09 January 2018
Patent Classes:
Current International Class:
H01L0217000000, H01L0270920000, H01L0218238000, H01L0297800000
17.
Clark, Lawrence T.; Kidd, David A.; Kuo, Augustine, "Integrated circuit device body bias circuits and methods"
Inventors:
Clark, Lawrence T.; Kidd, David A.; Kuo, Augustine
Abstract:
A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
28 October 2016
Grant Date:
26 December 2017
Patent Classes:
Current International Class:
H03K0170600000, H01L0270200000, G11C0051400000, H03K0030120000, G06F0175000000, G05F0032000000, H01L0270920000, G11C0050200000, H02M0030700000
18.
Thompson, Scott E.; Clark, Lawrence T., "Digital circuits having improved transistors, and methods therefor"
Inventors:
Thompson, Scott E.; Clark, Lawrence T.
Abstract:
Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
06 April 2017
Grant Date:
05 December 2017
Patent Classes:
Current International Class:
H01L0250000000, H03K0190000000, H01L0291000000, H01L0271180000, G11C0114120000
19.
Zhao, Dalong; Bakhishev, Teymur; Scudder, Lance; Gregory, Paul E.; Duane, Michael; Sridharan, U. C.; Ranade, Pushkar; Shifren, Lucian; Hoffmann, Thomas, "Semiconductor structure with multiple transistors having various threshold voltages"
Inventors:
Zhao, Dalong; Bakhishev, Teymur; Scudder, Lance; Gregory, Paul E.; Duane, Michael; Sridharan, U. C.; Ranade, Pushkar; Shifren, Lucian; Hoffmann, Thomas
Abstract:
A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
30 January 2017
Grant Date:
07 November 2017
Patent Classes:
Current International Class:
H01L0296600000, H01L0212650000, H01L0212830000, H01L0218234000, H01L0270880000
20.
Scudder, Lance; Ranade, Pushkar; Stager, Charles; Sridharan, Urupattur C.; Zhao, Dalong, "Reducing or eliminating pre-amorphization in transistor manufacture"
Inventors:
Scudder, Lance; Ranade, Pushkar; Stager, Charles; Sridharan, Urupattur C.; Zhao, Dalong
Abstract:
A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
20 October 2016
Grant Date:
17 October 2017
Patent Classes:
Current International Class:
H01L0214250000, H01L0218238000, H01L0212650000, H01L0296600000, H01L0291000000, H01L0210400000, H01L0218200000, H01L0210200000, H01L0270920000, H01L0297800000
21.
Bakhishev, Teymur; Wang, Lingquan; Zhao, Dalong; Ranade, Pushkar; Thompson, Scott E., "Buried channel deeply depleted channel transistor"
Inventors:
Bakhishev, Teymur; Wang, Lingquan; Zhao, Dalong; Ranade, Pushkar; Thompson, Scott E.
Abstract:
Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
04 October 2016
Grant Date:
10 October 2017
Patent Classes:
Current International Class:
H01L0297600000, H01L0299400000, H01L0310620000, H01L0311130000, H01L0311190000, H01L0271460000, H01L0297800000, H01L0291000000, H04N0053745000
22.
Clark, Lawrence T.; Thompson, Scott E.; Roy, Richard S.; Rogenmoser, Robert; Thummalapally, Damodar R., "Integrated circuit devices and methods"
Inventors:
Clark, Lawrence T.; Thompson, Scott E.; Roy, Richard S.; Rogenmoser, Robert; Thummalapally, Damodar R.
Abstract:
An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
21 April 2016
Grant Date:
22 August 2017
Patent Classes:
Current International Class:
G11C0110000000, G11C0114120000, G11C0070200000, G11C0114190000, H01L0271100000, H01L0297800000, H01L0291000000, G11C0050600000, G11C0051400000, G11C0114170000, G11C0114180000, H01L0290600000, H01L0291670000, H01L0270200000
23.
Boling, Edward J., "Power up body bias circuits and methods"
Inventors:
Boling, Edward J.
Abstract:
An integrated circuit device can include at least a first body bias circuit configured to generate a first body bias voltage different from power supply voltages of the IC device; at least a first bias control circuit configured to set a first body bias node to a first power supply voltage, and subsequently enabling the first body bias node to be set to the first body bias voltage; and a plurality of first transistors having bodies connected to the first body bias node.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
25 July 2014
Grant Date:
18 July 2017
Patent Classes:
Current International Class:
H03K0030100000, G05F0032000000
24.
Kidd, David A., "Tipless transistors, short-tip transistors, and methods and circuits therefor"
Inventors:
Kidd, David A.
Abstract:
An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
10 June 2016
Grant Date:
28 February 2017
Patent Classes:
Current International Class:
H01L0270880000, H01L0291000000, H01L0297800000, G11C0070800000, H03K0050600000, H03K0033560000, H03L0070800000
25.
Bakhishev, Teymur; Pradhan, Sameer; Hoffmann, Thomas; Sonkusale, Sachin R., "Method for fabricating a transistor device with a tuned dopant profile"
Inventors:
Bakhishev, Teymur; Pradhan, Sameer; Hoffmann, Thomas; Sonkusale, Sachin R.
Abstract:
A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. Different transistor devices with similar boron implants may be fabricated with different peak locations and heights for their respective dopant profiles by tailoring the carbon implant energy to effect tuned dopant profiles for the boron.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
25 February 2016
Grant Date:
21 February 2017
Patent Classes:
Current International Class:
H01L0213360000, H01L0291000000, H01L0212650000, H01L0296600000, H01L0297800000, H01L0210200000
26.
Clark, Lawrence T.; Kidd, David A.; Kuo, Augustine, "Integrated circuit device body bias circuits and methods"
Inventors:
Clark, Lawrence T.; Kidd, David A.; Kuo, Augustine
Abstract:
A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
15 July 2015
Grant Date:
17 January 2017
Patent Classes:
Current International Class:
G05F0032000000, G11C0051400000, H03K0170600000, H03K0030120000, G06F0175000000, H01L0270920000, G11C0050200000
27.
Scudder, Lance S.; Ranade, Pushkar; Stager, Charles; Sridharan, Urupattur C.; Zhao, Dalong, "Reducing or eliminating pre-amorphization in transistor manufacture"
Inventors:
Scudder, Lance S.; Ranade, Pushkar; Stager, Charles; Sridharan, Urupattur C.; Zhao, Dalong
Abstract:
A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
20 January 2015
Grant Date:
06 December 2016
Patent Classes:
Current International Class:
H01L0214250000, H01L0210400000, H01L0212650000, H01L0218200000, H01L0291000000, H01L0296600000, H01L0210200000, H01L0218238000
28.
Shifren, Lucian; Ranade, Pushkar; Gregory, Paul E.; Sonkusale, Sachin R.; Zhang, Weimin; Thompson, Scott E., "Advanced transistors with punch through suppression"
Inventors:
Shifren, Lucian; Ranade, Pushkar; Gregory, Paul E.; Sonkusale, Sachin R.; Zhang, Weimin; Thompson, Scott E.
Abstract:
An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5¿10(sup)18 dopant atoms per cm(sup)3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
22 December 2015
Grant Date:
29 November 2016
Patent Classes:
Current International Class:
H01L0291000000, H01L0270920000, H01L0290800000, H01L0293600000, H01L0218234000, H01L0270880000, H01L0296600000, H01L0297800000
29.
Shifren, Lucian; Ranade, Pushkar; Thompson, Scott E.; Sonkusale, Sachrin R.; Zhang, Weimin, "Low power semiconductor transistor structure and method of fabrication thereof"
Inventors:
Shifren, Lucian; Ranade, Pushkar; Thompson, Scott E.; Sonkusale, Sachrin R.; Zhang, Weimin
Abstract:
A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sV(sub)T compared to conventional bulk CMOS and can allow the threshold voltage V(sub)T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
19 August 2013
Grant Date:
15 November 2016
Patent Classes:
Current International Class:
H01L0217000000, H01L0270920000, H01L0218238000
30.
Bakhishev, Teymur; Wang, Lingquan; Zhao, Dalong; Ranade, Pushkar; Thompson, Scott E., "Buried channel deeply depleted channel transistor"
Inventors:
Bakhishev, Teymur; Wang, Lingquan; Zhao, Dalong; Ranade, Pushkar; Thompson, Scott E.
Abstract:
Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.
Assignee:
MIE FUJITSU SEMICONDUCTOR LTD
Filing Date:
23 May 2014
Grant Date:
25 October 2016
Patent Classes:
Current International Class:
H01L0213360000, H01L0271460000, H01L0297800000, H01L0296600000
