Abstract:
Accurate measurement of MOS transistor inversion capacitance with a physical silicon dioxide thickness less than 20 /spl Aring/ requires correction for the direct tunneli...Show MoreMetadata
Abstract:
Accurate measurement of MOS transistor inversion capacitance with a physical silicon dioxide thickness less than 20 /spl Aring/ requires correction for the direct tunneling leakage. This work presents a capacitance model and extraction based on the application of a lossy transmission line model to the MOS transistor. This approach properly accounts for the leakage current distribution along the channel and produces a gate length dependent correction factor for the measured capacitance that overcomes discrepancies produced through use of previously reported discrete element based models. An extraction technique is presented to determine the oxide's tunneling and channel resistance of the transmission line equivalent circuit. This model is confirmed by producing consistent C/sub 0x/ measurements for several different gate lengths with physical silicon dioxide thickness of 9, 12, and 18 /spl Aring/.
Published in: IEEE Electron Device Letters ( Volume: 21, Issue: 9, September 2000)
DOI: 10.1109/55.863109
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Cites in Papers - IEEE (35)
Select All
1.
René Berktold, Jochen Mannhart, "Two-Port-Network-Based Method to Measure Electrical Characteristics of MIS Devices With Ultrathin Barriers", IEEE Transactions on Electron Devices, vol.64, no.6, pp.2625-2628, 2017.
2.
Yonghun Kim, Young Gon Lee, Ukjin Jung, Jin Ju Kim, Minhyeok Choe, Kyong Taek Lee, Sangwoo Pae, Jongwoo Park, Byoung Hun Lee, "Extraction of Effective Mobility from nMOSFETs With Leaky Gate Dielectric Using Time Domain Reflectometry", IEEE Transactions on Electron Devices, vol.62, no.4, pp.1092-1097, 2015.
3.
Kyle M. Bothe, Peter A. von Hauff, Amir Afshar, Ali Foroughi-Abari, Kenneth C. Cadien, Douglas W. Barlage, "Capacitance Modeling and Characterization of Planar MOSCAP Devices for Wideband-Gap Semiconductors With High-$\kappa$ Dielectrics", IEEE Transactions on Electron Devices, vol.59, no.10, pp.2662-2666, 2012.
4.
Liu Hongxia, Kuang Qianwei, Luan Suzhen, Hao Yue, Zhao Aaron, Tallavarjula Sai, "Investigation of frequency dispersion effect in HfO2/SiO2 Gate Stack", 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, pp.245-247, 2009.
5.
Y. Wang, Kin P. Cheung, R. Choi, B.-H. Lee, "An Accurate Capacitance–Voltage Measurement Method for Highly Leaky Devices—Part II", IEEE Transactions on Electron Devices, vol.55, no.9, pp.2437-2442, 2008.
6.
Y. Wang, Kin Ping Cheung, R. Choi, B.-H. Lee, "An Accurate $C$– $V$ Measurement Method for Highly Leaky Devices—Part I", IEEE Transactions on Electron Devices, vol.55, no.9, pp.2429-2436, 2008.
7.
Wei Lee, Pin Su, Ke-Wei Su, Chung-Shi Chiang, Sally Liu, "Investigation of Anomalous Inversion C–V Characteristics for Long-Channel MOSFETs With Leaky Dielectrics: Mechanisms and Reconstruction", IEEE Transactions on Semiconductor Manufacturing, vol.21, no.1, pp.104-109, 2008.
8.
Enrique San Andres, Luigi Pantisano, Javier Ramos, Philippe J. Roussel, Barry J. O'Sullivan, Mara Toledano-Luque, Stefan DeGendt, Guido Groeseneken, "Accurate Gate Impedance Determination on Ultraleaky MOSFETs by Fitting to a Three-Lumped-Parameter Model atFrequencies From DC to RF", IEEE Transactions on Electron Devices, vol.54, no.7, pp.1705-1712, 2007.
9.
Y. Wang, K. P. Cheung, R. Choi, G. A. Brown, B.-H. Lee, "Time-Domain-Reflectometry for Capacitance–Voltage Measurement With Very High Leakage Current", IEEE Electron Device Letters, vol.28, no.1, pp.51-53, 2007.
10.
Daokui He, Wuyun Quan, "Efficient Parameter Extraction Scheme in Ultra-Thin Gate Dielectric MOS Capacitor with Considerable Gate Leakage", 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, pp.1336-1338, 2006.
11.
F. Li, L.F. Register, M.M. Hasan, S.K. Banerjee, "A Program for Device Model Parameter Extraction from Gate Capacitance and Current of Ultrathin$hboxSiO_2$and High-$kappa$Gate Stacks", IEEE Transactions on Electron Devices, vol.53, no.9, pp.2118-2127, 2006.
12.
A.E. Islam, A. Haque, "Accumulation gate capacitance of MOS devices with ultrathin high-/spl kappa/ gate dielectrics: modeling and characterization", IEEE Transactions on Electron Devices, vol.53, no.6, pp.1364-1372, 2006.
13.
K. Dandu, Y. Saripalli, D. Braddock, M. Johnson, D.W. Barlage, "Characterization and modeling of AlGaN/GaN MOS capacitor with leakage for large signal transistor modeling", IEEE Microwave and Wireless Components Letters, vol.15, no.10, pp.664-666, 2005.
14.
Y.R. Wang, Y.W. Ying, Chien Hua Lung, W.T. Chiang, E. Hsu, M.F. Lu, C. Lin, R.F. Lou, L.Y. Cheng, C.P. Chen, M. Chan, O. Cheng, K.T. Huang, S.F. Tzou, S.W. Sun, "A novel fabrication process to downscale SiON gate dielectrics (EOT = 1.06 nm, Jgn = 8.5 A/cm/sup 2/) toward sub-65nm and beyond", Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., pp.164-165, 2005.
15.
P.A. Kraus, K.Z. Ahmed, C.S. Olsen, F. Nouri, "Model to predict gate tunneling current of plasma oxynitrides", IEEE Transactions on Electron Devices, vol.52, no.6, pp.1141-1147, 2005.
16.
Wei Lee, Ke-Wei Su, Chung-Shi Chiang, S. Liu, Pin Su, "Inversion MOS capacitance extraction for ultra-thin gate oxide using BSIM4", IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)., pp.62-63, 2005.
17.
J. Ramos, W. Jeamsaksiri, A. Mercha, S. Thijs, D. Linten, P. Wambacq, B. de Jaeger, I. Debusschere, S. Biesemans, S. Decoutere, "Hot-carrier degradation on the analogue/RF performances of a 90nm RF-CMOS technology demonstrated in a 900MHz low-power LNA", IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)., pp.64-65, 2005.
18.
Jung-Suk Goo, T. Mantei, K. Wieczorek, W.G. En, A.B. Icel, "Extending two-element capacitance extraction method toward ultraleaky gate oxides using a short-channel length", IEEE Electron Device Letters, vol.25, no.12, pp.819-821, 2004.
19.
O. Tonomura, Y. Shimamoto, H. Miki, S.-I. Saito, K. Torii, M. Hiratani, J. Yugami, "Accurate evaluation of mobility in high gate-leakage-current MOSFETs by using a transmission-line model", IEEE Transactions on Electron Devices, vol.51, no.10, pp.1653-1658, 2004.
20.
G.T. Sasse, R. de Kort, J. Schmitz, "Gate-capacitance extraction from RF C-V measurements [MOS device applications]", Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850), pp.113-116, 2004.
21.
T. Kunikiyo, T. Watanabe, T. Kanamoto, H. Asazato, M. Shirota, K. Eikyu, Y. Ajioka, H. Makino, K. Ishikawa, S. Iwade, Y. Inoue, "Test structure measuring inter- and intralayer coupling capacitance of interconnection with subfemtofarad resolution", IEEE Transactions on Electron Devices, vol.51, no.5, pp.726-735, 2004.
22.
J. Schmitz, F.N. Cubaynes, R.J. Havens, R. de Kort, A.J. Scholten, L.F. Tiemeijer, "Test structure design considerations for RF-CV measurements on leaky dielectrics", IEEE Transactions on Semiconductor Manufacturing, vol.17, no.2, pp.150-154, 2004.
23.
W. Jeamsaksiri, A. Mercha, J. Ramos, S. Decoutere, F.N. Cubaynes, "Optimal frequency range selection for full C-V characterization above 45MHz for ultra thin (1.2-nm) nitrided oxide MOSFETs", Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516), pp.297-301, 2004.
24.
K.Z. Ahmed, P.A. Kraus, C. Olsen, F. Nouri, "The evaluation of performance parameters of MOSFETs with alternative gate dielectrics", IEEE Transactions on Electron Devices, vol.50, no.12, pp.2564-2567, 2003.
25.
J. Yugami, S. Tsujikawa, R. Tsuchiya, S. Saito, Y. Shimamoto, K. Torii, T. Mine, T. Onai, "Advanced oxynitride gate dielectrics for CMOS applications", Extended Abstracts of International Workshop on Gate Insulator (IEEE Cat. No.03EX765), pp.140-145, 2003.
26.
P.A. Kraus, K.Z. Ahmed, C.S. Olsen, F. Nouri, "Physical models for predicting plasma nitrided Si-O-N gate dielectric properties from physical metrology", IEEE Electron Device Letters, vol.24, no.9, pp.559-561, 2003.
27.
K.Z. Ahmed, P.A. Kraus, C. Olsen, S. Hung, F. Nouri, "Observation of nitrogen-enhanced doping deactivation at the polysilicon-oxynitride interface of pMOSFETs with 12-/spl Aring/ gate dielectrics", IEEE Electron Device Letters, vol.24, no.7, pp.445-447, 2003.
28.
Hung-Der Su, Bi-Shiou Chiou, Shien-Yang Wu, Ming-Hsung Chang, Kuo-Hua Lee, Yung-Shun Chen, Chih-Ping Chao, Yee-Chaung See, J.Y.-C. Sun, "A floating well method for exact capacitance-voltage measurement of nano technology", IEEE Transactions on Electron Devices, vol.50, no.6, pp.1543-1544, 2003.
29.
O. Tonomura, Y. Shimamoto, K. Torii, M. Hiratani, S. Saito, J. Yugami, "Evaluation of mobility in the MOSFET with high leakage current", International Conference on Microelectronic Test Structures, 2003., pp.91-94, 2003.
30.
D. Rideau, P. Scheer, D. Roy, G. Gouget, M. Minondo, A. Juge, "Series resistance estimation and C(V) measurements on ultra thin oxide MOS capacitors", International Conference on Microelectronic Test Structures, 2003., pp.191-196, 2003.
Cites in Papers - Other Publishers (12)
1.
Ryun Na Kim, Hye Won Yun, Jinho Lee, Woo-Byoung Kim, "Dipole Formation and Electrical Properties According to SiO2 Layer Thickness at an Al2O3/SiO2 Interface", The Journal of Physical Chemistry C, 2021.
2.
Lei Han, Jie Pan, Qinglin Zhang, Shibin Li, Zhi Chen, "Atomic Layer Deposition of High Quality HfO2Using In-Situ Formed Hydrophilic Oxide as an Interfacial Layer", ECS Journal of Solid State Science and Technology, vol.3, no.12, pp.N155, 2014.
3.
Yonghun Kim, Seung-heon Chris Baek, Changhoon Jeon, Young Gon Lee, Jin Ju Kim, Ukjin Jung, Soo Cheol Kang, Woojin Park, Seok Hee Lee, Byoung Hun Lee, "Leakage current limit of time domain reflectometry in ultrathin dielectric characterization", Japanese Journal of Applied Physics, vol.53, no.8S1, pp.08LC02, 2014.
4.
Ajeesh M. Sahadevan, Kalon Gopinadhan, Charanjit S. Bhatia, Hyunsoo Yang, "Parallel-leaky capacitance equivalent circuit model for MgO magnetic tunnel junctions", Applied Physics Letters, vol.101, no.16, pp.162404, 2012.
5.
Md. Mahbub Satter, Ahmad Ehteshamul Islam, Dhanoop Varghese, Muhammad Ashraful Alam, Anisul Haque, "A self-consistent algorithm to extract interface trap states of MOS devices on alternative high-mobility substrates", Solid-State Electronics, vol.56, no.1, pp.141, 2011.
6.
Wei Lee, Pin Su, Ke-Wei Su, Chung-Shi Chiang, Sally Liu, "Investigation of Inversion Capacitance–Voltage Reconstruction for Metal Oxide Semiconductor Field Effect Transistors with Leaky Dielectrics using BSIM4/SPICE and Intrinsic Input Resistance Model", Japanese Journal of Applied Physics, vol.46, no.4B, pp.1870, 2007.
7.
Y. X. Li, L. Yan, R. P. Shrestha, D. Yang, E. A. Irene, "Study of poly(vinylidene fluoride-trifluoroethylene) as a potential organic high K gate dielectric", Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, vol.25, no.2, pp.275, 2007.
8.
C. Leroux, F. Allain, A. Toffoli, G. Ghibaudo, G. Reimbold, "Automatic statistical full quantum analysis of C-V and I-V characteristics for advanced MOS gate stacks", Microelectronic Engineering, vol.84, no.9-10, pp.2408, 2007.
9.
Carl Scharrer, Yuegang Zhao, "High-Frequency Capacitance Measurements for Monitoring EOT of Thin Gate Dielectrics", Measurement and Control, vol.39, no.1, pp.24, 2006.
10.
G.A. Brown, "Electrical Measurement Issues for Alternative Gate Stack Systems", High Dielectric Constant Materials, vol.16, pp.521, 2005.
11.
J. Schmitz, F.N. Cubaynes, R. de Kort, R. Havens, A.J. Scholten, L.F. Tiemeijer, "The RF-CV method for characterization of leaky gate dielectrics", Microelectronic Engineering, vol.72, no.1-4, pp.149, 2004.
12.
F. Gilibert, D. Rideau, S. Bernardini, P. Scheer, M. Minondo, D. Roy, G. Gouget, A. Juge, "DC and AC MOS transistor modelling in presence of high gate leakage and experimental validation", Solid-State Electronics, vol.48, no.4, pp.597, 2004.