Series resistance estimation and C(V) measurements on ultra thin oxide MOS capacitors

Based on measurements on test structures with various electrical silicon oxide thicknesses (from 21 /spl Aring/ to 13 /spl Aring/) and areas (from 27000 /spl mu/m/sup 2/ to 2 /spl mu/m/sup 2/), this paper describes the effect of gate current on measured capacitance using a standard 10 kHz-to-1 MHz LCR-meter. We show that, in presence of high gate leakage, the series impedance, and also the channel debiasing, have a dramatic effect on observed C(V) curves. We also propose a segmented-MOS model, allowing discrete solution of the current continuity equation along the channel, which fits the measured C(V) and provides a solution for process monitoring (such as oxide thickness) and intrinsic capacitance determination for device modeling.

Introduction

According to the ITRS [1] Silicon road map, the gate oxide used for high performance MOSFETs is rapidly scaled down to or below within the year 2003, giving rise to a tunnelling gate current exceeding10A/cm². Several observations report that this high leakage strongly affects the measured () characteristics [2]–[5]. A precise intrinsic MOSFET capacitance determination is though an essential issue for device modeling or process monitoring since first order parameters (such as gate oxide thickness) are extracted from () curves [6].