A floating well method for exact capacitance-voltage measurement of nano technology

Small gate area with short gate length reduces the C-V distortion of ultrathin oxide devices, but results in high parasitic capacitance/total capacitance ratio. The floating well method can exclude the parasitic capacitance to obtain accurate inversion oxide thickness without using any dummy pattern. It is suitable for nano technology.

I. Introduction

In nano technology, the oxide thickness is scaled down to meet the performance requirements [1]. The capacitance-voltage (–) curve of ultra-thin oxide is distorted due to large gate leakage current [2]. The distortion of high-frequency – curve of ultra-thin oxide has been characterized by circuit approach by considering the gate leakage current and channel resistance [3]–[6]. The smaller pattern area (25 ) with lower channel resistance is used in this paper to minimize the high frequency – distortion. Hence, since the bonding pad area is restricted by bonding and probing technology, the parasitic capacitance contributed by bonding pad can not be reduced with the capacitance of test pattern. Hence, larger EOT extraction error can be induced by parasitic capacitance when smaller pattern area is employed. In this paper, a – measurement method with floating well proposed this paper enables to measure the gate-to-channel capacitance between source-drain and gate electrode in order to suppress the offset capacitance when measured the gate-to-body capacitance . The accurate EOT of nano technology can be extracted by inversion capacitance measured with floating well method without any dummy pattern. Fig. 1.

Oxide thickness dependence of device – curves. Arrows indicate the occurrence of – distortion, i.e., V or V for nm; V or V for nm.

Fig. 2.

Pattern area dependence of device – curves with and without dummy pattern calibration.