Efficient Parameter Extraction Scheme in Ultra-Thin Gate Dielectric MOS Capacitor with Considerable Gate Leakage

Presented herein is a fast but accurate quantum C-V simulation, capable of extracting effective oxide thickness and other parameters based strictly on C-V data alone. The apparent C-V degradation in leaky dielectric MOSFETs is shown mitigated in sub-micrometer channel length device because of the diminished channel resistance and gate leakage

1. Introduction

The ultra-thin gate dielectric required for nm CMOS gives rise to a large gate leakage. The leakage, coupled with the channel resistance, drastically modifies the C-V behavior [1]–[5]. This anomalous C-V data was quantified by introducing distributed RC network [1]–[5] for the leakage path of the gate current, .