An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory | IEEE Conference Publication | IEEE Xplore

An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory


Abstract:

We demonstrate a novel phase change memory cell utilizing doped Ge nanowire pn-junction diode both as a bottom electrode and a memory cell selection device. This memory c...Show More

Abstract:

We demonstrate a novel phase change memory cell utilizing doped Ge nanowire pn-junction diode both as a bottom electrode and a memory cell selection device. This memory cell can be used for a cross-point memory array with diode selection. Using selective growth of isolated vertical nanowires in each cell, we have minimized the contact area below the lithography limit. A very low SET programming current of 10's of μA was achieved. RESET/SET resistance ratio of 100x was obtained. The diode provides 100x isolation between forward and reverse bias in the SET state.
Date of Conference: 12-14 June 2007
Date Added to IEEE Xplore: 08 October 2007
Print ISBN:978-4-900784-03-1

ISSN Information:

Conference Location: Kyoto, Japan
Citations are not available for this document.

Introduction

Cross-point memory with 4F2 cell is ideal for high density memory. To ensure adequate sense margin, a diode must be integrated at each cross-point to eliminate the leakage current through the half-selected cells (Fig. 1). In this paper, we demonstrate, for the first time, a pn-junction diode integrated with a phase change memory cell. The large programming currents needed in phase change memory require large access device widths. This is a major obstacle that must be overcome to fully utilize intrinsic superb scalability of phase change material [1]. Many ideas have been proposed to reduce the bottom electrode contact area and therefore reduce the programming current. These include edge contact [2], lateral cell [3], and trench cell [4]. Compared to these methods, the nanowire bottom electrode contact approach [5] can easily provide a small contact area due to the small diameter of the nanowire. In this paper, we use phosphorus doped germanium nanowires (GeNW) as the bottom electrode contact (BEC). At the same time, the n-doped nanowire forms a pn junction with the p-type substrate. This nanowire pn-junction diode plus phase change memory cell combination results in a low programming current and eliminates the leakage current of half-selected cells. The size of nanowire is determined by the catalyst volume and growth condition, which can be reduced below the lithographic limit. Schematic of PCM memory arrays with nanowire diodes as memory cell selelction devices. The upper right array is without the diodes, which has leakage paths due to half-selected memory cells. The lower right array with diodes eliminates the leakage paths.

Cites in Papers - |

Cites in Papers - IEEE (14)

Select All
1.
Taeung No, Seonjun Choi, Gaeryun Sung, Seong-Beom Kim, Jaeduk Han, Yun-Heub Song, "A Discharge-Path-Based Sensing Circuit With OTS Snapback Current Protection for Phase Change Memories", IEEE Access, vol.10, pp.53513-53521, 2022.
2.
Li Sun, Nan Zheng, Tao Zhang, Pinaki Mazumder, "Fault Modeling and Parallel Testing for 1T1M Memory Array", IEEE Transactions on Nanotechnology, vol.17, no.3, pp.437-451, 2018.
3.
Jason K. Eshraghian, Kyoung-Rok Cho, Herbert H. C. Iu, Tyrone Fernando, Nicolangelo Iannella, Sung-Mo Kang, Kamran Eshraghian, "Maximization of Crossbar Array Memory Using Fundamental Memristor Theory", IEEE Transactions on Circuits and Systems II: Express Briefs, vol.64, no.12, pp.1402-1406, 2017.
4.
Yang Zheng, Cong Xu, Yuan Xie, "Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues", The 20th Asia and South Pacific Design Automation Conference, pp.112-117, 2015.
5.
Pierre-Emmanuel Gaillardon, Davide Sacchetto, Giovanni Betti Beneventi, M. Haykel Ben Jamaa, Luca Perniola, Fabien Clermidy, Ian O’Connor, Giovanni De Micheli, "Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs", IEEE Transactions on Nanotechnology, vol.12, no.1, pp.40-50, 2013.
6.
Xiangyu Dong, Cong Xu, Yuan Xie, Norman P. Jouppi, "NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.31, no.7, pp.994-1007, 2012.
7.
Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie, "A frequent-value based PRAM memory architecture", 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pp.211-216, 2011.
8.
M. Haykel Ben Jamaa, Gianfranco Cerofolini, Giovanni De Micheli, Yusuf Leblebici, "Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique", IEEE Transactions on Nanotechnology, vol.10, no.4, pp.891-899, 2011.
9.
Pierre-Emmanuel Gaillardon, M. Haykel Ben-Jamaa, Giovanni Betti Beneventi, Fabien Clermidy, Luca Perniola, "Emerging memory technologies for reconfigurable routing in FPGA architecture", 2010 17th IEEE International Conference on Electronics, Circuits and Systems, pp.62-65, 2010.
10.
Jiale Liang, H.-S. Philip Wong, "Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies", IEEE Transactions on Electron Devices, vol.57, no.10, pp.2531-2538, 2010.
11.
Guangyu Sun, Yongsoo Joo, Yibo Chen, Dimin Niu, Yuan Xie, Yiran Chen, Hai Li, "A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement", HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture, pp.1-12, 2010.
12.
Shu Li, Tong Zhang, "Exploratory study on circuit and architecture design of very high density diode-switch phase change memories", 2009 10th International Symposium on Quality Electronic Design, pp.424-429, 2009.
13.
Stefan Lai, "Non-volatile memory technologies: The quest for ever lower cost", 2008 IEEE International Electron Devices Meeting, pp.1-6, 2008.
14.
SangBum Kim, Yuan Zhang, James P. McVittie, Hemanth Jagannathan, Yoshio Nishi, H.-S. Philip Wong, "Integrating Phase-Change Memory Cell With Ge Nanowire Diode for Crosspoint Memory—Experimental Demonstration and Analysis", IEEE Transactions on Electron Devices, vol.55, no.9, pp.2307-2313, 2008.

Cites in Papers - Other Publishers (18)

1.
EJAZ AHMAD KHERA, HAFEEZ ULLAH, MUHAMMAD IMRAN, HASSAN ALGADI, FAYYAZ HUSSAIN, RANA MUHAMMAD ARIF KHALIL, "THE FIRST PRINCIPLE STUDY OF COMPARISON OF DIVALENT AND TRIVALENT IMPURITY IN RRAM DEVICES USING GGA+U", Surface Review and Letters, vol.28, no.06, pp.2150039, 2021.
2.
Sang Hyun Sung, Do Hyun Kim, Tae Jin Kim, Il?Suk Kang, Keon Jae Lee, "Unconventional Inorganic?Based Memristive Devices for Advanced Intelligent Systems", Advanced Materials Technologies, vol.4, no.4, pp.1900080, 2019.
3.
V. Cientanni, W. I. Milne, M. T. Cole, Micro and Nanomanufacturing Volume II, pp.1, 2018.
4.
"3D Cross‐Point Array Memory", Vertical 3D Memory Technologies, pp.192, 2014.
5.
Xiangyu Dong, Norman P. Jouppi, Yuan Xie, "A Circuit-Architecture Co-optimization Framework for Exploring Nonvolatile Memory Hierarchies", Emerging Memory Technologies, pp.261, 2014.
6.
Xiangyu Dong, Cong Xu, Norm Jouppi, Yuan Xie, "NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Non-volatile Memory", Emerging Memory Technologies, pp.15, 2014.
7.
Guangyu Sun, "Replacing Different Levels of the Memory Hierarchy with NVMs", Exploring Memory Hierarchy Design with Emerging Memory Technologies, vol.267, pp.13, 2014.
8.
Guangyu Sun, Yongsoo Joo, Yibo Chen, Yiran Chen, Yuan Xie, Emerging Memory Technologies, pp.51, 2014.
9.
Guangyu Sun, Exploring Memory Hierarchy Design with Emerging Memory Technologies, vol.267, pp.1, 2014.
10.
Xiangyu Dong, Norman P. Jouppi, Yuan Xie, "A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies", ACM Transactions on Architecture and Code Optimization, vol.10, no.4, pp.1, 2013.
11.
Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi, "Hybrid checkpointing using emerging nonvolatile memories for future exascale systems", ACM Transactions on Architecture and Code Optimization, vol.8, no.2, pp.1, 2011.
12.
M. Haykel Ben Jamaa, Giovanni De Micheli, Nanoelectronic Circuit Design, pp.153, 2011.
13.
M. Haykel Ben Jamaa, Regular Nanofabrics in Emerging Technologies, vol.82, pp.33, 2011.
14.
"Future Paths of Innovation", Silicon Non‐Volatile Memories, pp.171, 2009.
15.
Pascal O Vontobel, Warren Robinett, Philip J Kuekes, Duncan R Stewart, Joseph Straznicky, R Stanley Williams, "Writing to and reading from a nano-scale crossbar memory based on memristors", Nanotechnology, vol.20, no.42, pp.425204, 2009.
16.
Xiangyu Dong, Naveen Muralimanohar, Norm Jouppi, Richard Kaufmann, Yuan Xie, "Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems", Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, pp.1-12, 2009.
17.
M. Haykel Ben Jamaa, Yusuf Leblebici, Giovanni De Micheli, "Decoding nanowire arrays fabricated with the Multi-Spacer Patterning Technique", 2009 46th ACM/IEEE Design Automation Conference, pp.77-82, 2009.

References

References is not available for this document.