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An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory | IEEE Conference Publication | IEEE Xplore

An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory


Abstract:

We demonstrate a novel phase change memory cell utilizing doped Ge nanowire pn-junction diode both as a bottom electrode and a memory cell selection device. This memory c...Show More

Abstract:

We demonstrate a novel phase change memory cell utilizing doped Ge nanowire pn-junction diode both as a bottom electrode and a memory cell selection device. This memory cell can be used for a cross-point memory array with diode selection. Using selective growth of isolated vertical nanowires in each cell, we have minimized the contact area below the lithography limit. A very low SET programming current of 10's of μA was achieved. RESET/SET resistance ratio of 100x was obtained. The diode provides 100x isolation between forward and reverse bias in the SET state.
Date of Conference: 12-14 June 2007
Date Added to IEEE Xplore: 08 October 2007
Print ISBN:978-4-900784-03-1

ISSN Information:

Conference Location: Kyoto, Japan
Stanford University, Stanford, CA, US
Stanford University, Stanford, CA, US
Stanford University, Stanford, CA, US
Stanford University, Stanford, CA, US
Department of Electrical Engineering, University of Stanford, Stanford, CA, USA
Department of Electrical Engineering, University of Stanford, Stanford, CA, USA
Stanford University, Stanford, CA, US
Stanford University, Stanford, CA, US

Introduction

Cross-point memory with 4F2 cell is ideal for high density memory. To ensure adequate sense margin, a diode must be integrated at each cross-point to eliminate the leakage current through the half-selected cells (Fig. 1). In this paper, we demonstrate, for the first time, a pn-junction diode integrated with a phase change memory cell. The large programming currents needed in phase change memory require large access device widths. This is a major obstacle that must be overcome to fully utilize intrinsic superb scalability of phase change material [1]. Many ideas have been proposed to reduce the bottom electrode contact area and therefore reduce the programming current. These include edge contact [2], lateral cell [3], and trench cell [4]. Compared to these methods, the nanowire bottom electrode contact approach [5] can easily provide a small contact area due to the small diameter of the nanowire. In this paper, we use phosphorus doped germanium nanowires (GeNW) as the bottom electrode contact (BEC). At the same time, the n-doped nanowire forms a pn junction with the p-type substrate. This nanowire pn-junction diode plus phase change memory cell combination results in a low programming current and eliminates the leakage current of half-selected cells. The size of nanowire is determined by the catalyst volume and growth condition, which can be reduced below the lithographic limit. Schematic of PCM memory arrays with nanowire diodes as memory cell selelction devices. The upper right array is without the diodes, which has leakage paths due to half-selected memory cells. The lower right array with diodes eliminates the leakage paths.

Stanford University, Stanford, CA, US
Stanford University, Stanford, CA, US
Stanford University, Stanford, CA, US
Stanford University, Stanford, CA, US
Department of Electrical Engineering, University of Stanford, Stanford, CA, USA
Department of Electrical Engineering, University of Stanford, Stanford, CA, USA
Stanford University, Stanford, CA, US
Stanford University, Stanford, CA, US

References

References is not available for this document.