James McVittie - IEEE Xplore Author Profile

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Nanometric scaling steadily increases failure rates, which are particularly acute for ultimate complementary metal–oxide–semiconductor (CMOS) and post-CMOS devices. We previously established an ECC-based method of memory repair that dramatically reduced the cost for high fault rates, and in this article, we establish a repair architecture that further reduces the power cost. Since CAMs are power h...Show More
Silicon-based CMOS technologies are fast approaching their ultimate limits. By approaching these limits, fabrication yield, reliability, and power densities, worsen steadily making further nanometric scaling increasingly difficult. These problems would become showstoppers in ultimate-CMOS and post-CMOS technologies, unless efficient fault-mitigation and low-power approaches are developed to mainta...Show More
Memory system reliability is a serious concern in many systems today and is becoming more worrisome as technology scales, system size grows and the demand of aggressive voltage reduction becomes more stringent. Thus, disposing of memory repair architectures with strong fault tolerance capability at low cost is desirable. In this context, Error Correcting Codes (ECC)-based repair techniques were pr...Show More
In modern SoCs embedded memories should be protected by ECC against field failures to achieve acceptable reliability. They should also be repaired after fabrication to achieve acceptable fabrication yield, as well as during lifetime to increase lifespan. In technologies affected by high defect densities, conventional repair induces very high cost. To reduce it, in previous work we proposed the ECC...Show More
Networks-on-Chips (NoCs) are considered to be the paradigm of choice for on-chip communication and are today widely adopted in many-core systems. Many existing routing solutions make use of virtual channels (VCs) to avoid deadlocks while offering enough routing flexibility to avoid faulty and congested areas in a NoC. However, most of the current solutions rely on an overly restrictive, static par...Show More
The double sampling paradigm is an efficient method to protect the circuits against soft-errors. But the data that are going out of the area protected by double sampling are still vulnerable. In this paper we proposed an architectural solution that uses three latches to remove those constraints and protect the area outside the double sampling domain without adding a buffer stage.Show More
In nanometer technologies, circuits are more and more sensitive to various kinds of perturbations. Alpha particles and atmospheric neutrons induce single-event upsets, affecting memory cells, latches, and flip-flops. They also induce single-event transients, initiated in the combinational logic and captured by the latches and flip-flops associated with the outputs of this logic. In the past, the m...Show More
3D integration opens up new opportunities for future multiprocessor chips by enabling fast and highly scalable 3D Network-on-Chip (NoC) topologies. However, in an aim to reduce the cost of Through-silicon via (TSV), partially vertically connected NoCs, in which only a few vertical TSV links are available, have been gaining relevance. In addition, the number of vertical paths can be expected to be ...Show More
In nanometer technologies, circuits are more and more sensitive to various kinds of perturbations. Alpha particles and atmospheric neutrons are affecting storage elements as well as the combinational logic. In the past, the major efforts were related on memories. However, as the whole situation is getting worse, solutions that protect the entire design are mandatory. Solutions for detecting the er...Show More
With NoCs (Networks-on-Chips) becoming a central part of today's many-core systems, ensuring a good level of performance at the routing level has never been so crucial. In previous works, we have introduced a novel method for designing fully adaptive deadlock-free routing algorithms for NoCs called ESPADA (EScape PAths with Dynamic channel Acquisition). The strength of our approach lies in its abi...Show More
As the number of processing elements in modern chips keeps increasing, the evaluation of new designs will need to account for various challenges at the NoC level. To cope with the impractically long run times when simulating large NoCs, we introduce a novel GPU-based parallel simulation method that can speed up simulations by over 250×, while offering RTL-like accuracy. These promising results mak...Show More
NoCs (Networks-on-chips) are considered as the paradigm of choice for on-chip communication as they solve the scalability concerns of traditional buses. Many research efforts have been aimed toward the design of adaptive routing algorithms that are flexible enough to avoid congested and defective areas in a NoC. However, to avoid deadlocks, most of these solutions either prohibit some turns, which...Show More
Aggressive technology scaling has dramatic impact on process, voltage and temperature (PVT) variations; circuit aging and wearout; clock skews; sensitivity to EMI (e.g. crosstalk and ground bounce), sensitivity to radiation-induced SEUs SETs; as well as power dissipation and thermal constraints. The resulting high defect rates and design complexity, adversely affect fabrication yield and reliabili...Show More
NoCs (Networks-on-Chips) are being viewed as the paradigm of choice for on-chip communication in modern SoCs (Systems-on-chips). Unfortunately, continuous technology downscaling is rendering NoC components increasingly susceptible to failure, to a point where it is no longer an option to design such systems without accounting for reliability issues. In this work, we concern ourselves with faults a...Show More
In modern SoCs embedded memories should be protected by ECC against field failures to achieve acceptable reliability. They should also be repaired after fabrication to achieve acceptable fabrication yield. In technologies affected by high defect densities, conventional repair induces very high costs. To reduce it, we can use ECC-based repair, consisting in using the ECC for fixing words comprising...Show More
NoCs (Networks-on-Chip) are an attractive alternative to communication buses for SoCs (Systems-on-Chip) as they offer both high scalability and low power consumption. However, designing such systems in the nanoscale era brings up some serious concerns about reliability. Our aim is to design robust NoCs while limiting performance degradation. In this paper, we introduce several techniques meant to ...Show More
We illustrate that memory repair for high fault rates can be exploited for improving yield, extending lifetime, reducing power, and improving reliability, and consequently can be used to push aggressively the limits of technology scaling. We also present recent advances in low-area and low-power memory repair for high fault rates. As one of our main goals is to use this repair for reducing as much...Show More
We illustrate that memory repair for high defect densities allows improving yield, extending circuit life, reducing power, and improving reliability, and can be used to push aggressively the limits of technology scaling. Then we present several developments enabling low-cost memory repair for high defect densities, which alllow realising this promise.Show More
Aggressive technology scaling impacts dramatically parametric yield, life-span, and reliability of circuits fabricated in advanced nanometric nodes. These issues may become showstoppers when scaling deeper to the sub-10-nm domain. To mitigate them, various approaches have been proposed, including increasing guard bands, fault-tolerant design, and canary circuits. Each of them is subject to several...Show More
Single-event transients (SETs) remain a concern in field-programmable gate arrays (FPGAs) used for space applications. However, accurate measurement of SETs in FPGAs is challenging. This paper describes a calibrated circuit for on-chip measurement of SETs with a temporal precision better than one gate delay. In addition, a technique to measure the final effect of SETs in clocked, complex circuits ...Show More
New CMOS processes offer cheaper but less reliable transistors. This trend foreshadows the apparition of processors consisting of hundreds and thousands of cores prone to defects. In this context, the performance of the core interconnect under faults will be critical. In this work, we propose the combination of a novel adaptive routing algorithm and several related router mechanisms, which firstly...Show More
Aggressive technology scaling impacts dramatically parametric yield and reliability in advanced nanometric nodes, and can become showstoppers when moving deeper to the sub-10nm domain. To mitigate this issue various approaches have been proposed including increasing guard-bands, fault-tolerant design, and canary circuits. Each of these approaches have certain fundamental drawbacks such as: large p...Show More
The integration of more and more computing cores into processors drives the adoption of larger and larger Network-on-Chips (NoCs). Concurrently, the decreasing reliability of 1 the latest technologies promotes the utilization of fault-tolerant techniques. Unfortunately, the understanding of fault-tolerant NoCs is increasingly difficult as interconnect scale up, because they require the combination...Show More
Embedded memories occupy the largest part of modern SoCs and include an even larger amount of transistors. As memories are designed very tightly to the technology limits, they are more prone to failures than other circuits. Thus, they concentrate the large majority of fabrication defects affecting yield adversely. Defect densities are expected to sharply increase in ultimate CMOS and post CMOS pro...Show More
The coming era of chips consisting of billions of gates foreshadows processors containing thousands of unreliable cores. In this context, high energy efficiency will be available, under the constraint that applications leverage the large amount of computing cores, while masking frequent faults of the chip. In this paper, an high-level method is proposed to map and manage a parallel application on ...Show More