Impact of Gaussian Grain Boundary Trap States on the Performance of the LTPS TFTs

This paper presents a study on the impact of grain boundary trap states on the performance of polysilicon thin-film transistors (TFTs. It uses the Synopsys TCAD tool to analyze the device behavior of low-temperature polysilicon (LTPS) TFTs. It has been observed that grain boundary traps in polycrystalline material adversely impact the threshold voltage, subthreshold slope, and mobility. Across the grain boundaries, the primary transport mechanism is thermionic emission and it limits the carrier mobility and carrier concentration. Moreover, it was found that the influence of grain boundary traps was less in TFTs employing high-κ gate dielectrics. With HfO2 gate dielectric the simulated device exhibited the least threshold voltage of 0.85 V, the least subthreshold slope of 80 mV/decade, the highest field-effect mobility of 41 cm²/V-s, and a best on-to-off current ratio of 1.93x10⁸ compared to the TFTs with SiO2 and Si3N4 gate dielectric.

I. Introduction

Ultrahigh-performance polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) are in high demand for small and medium-size displays with integrated systems on a glass substrate such as multifunctional cellular phones, personal data acquisition systems, and sheet computers [1]–[3]. Based upon LTPS TFTs, several exploratory circuits including a central processing unit (CPU), dynamic random-access memory (DRAM), radio frequency identification (RFID), low-voltage differential signal (LVDS) receivers, and microwave low-noise amplifiers (LNAs) have already been demonstrated [4], [5]. An excimer laser-annealing (ELA) method using a thin beam has been widely used for mass-producing poly-Si films [4]. However, the LTPS TFTs on these films are not satisfactory in their performance for the above-mentioned high-end applications because in poly-Si film grains are typically as small as 0.3 – 0.5 mm in diameter, and thus the TFT channel region contains several grain boundaries. Carriers are frequently scattered by the grain boundaries present in the channel, leading to low mobility and low carrier concentration [6]–[9]. Therefore, various advanced crystallization methods have been developed to grow long grains so that grains much longer than the TFT feature size can be grown. In terms of the LTPS TFT device analysis, the presence of grain boundaries cannot be neglected. Hossain et al. [7], proposed a model for carrier transport in the TFTs by assuming all kinds of defects including the defects in polycrystalline channel material and the interface defects at gate dielectric and semiconductor interface can be assumed to be localized in grain boundaries (GBs). The distribution follows a Gaussian Profile with a peak trap density at the middle of the energy bandgap. The characteristic decay energy E₁ and E₂ of the defects in the GBs are assumed to be material constant. The polycrystalline thin film of LTPS is defined by equally spaced GBs perpendicular to the direction of carriers. The GB is modeled as a thin layer having acceptor and donor-type states with Gaussian distribution [10].