Effect of deep and tail grain boundary trap states on the performance of poly-ZnO TFT

The presence of grain boundaries in polycrystalline ZnO hugely impacts its electrical characteristic. In this work, we have studied the influence of double exponential grain boundary (GB) traps on the performance of a ZnO TFT. It is assumed that all kinds of defects in the ZnO/ gate-dielectric interface and GB are effectively localized in GB traps. Moreover, traps are thermally activated as per the multiple trapping and release (MTR) theory. Using Sentaurus TCAD, the device's behavior has been analyzed and it has been found that the ZnO TFT employing high-κ gate-dielectric exhibits minimal degradation in TFT characteristics in the presence of traps. In the presence of deep state traps, Ndeep =1 ×10¹⁰ cm⁻²eV⁻¹ and tail state traps Ntail = 2.85 × 10¹³ cm⁻²eV⁻¹, TFT with gate-dielectric HfO2 exhibited least threshold voltage of 0.44 V & a subthreshold slope of 96 mV, and the highest field-effect mobility of 3.6 cm²/V − s compared to TFT with SiO2 and Si3N4 gate-dielectric.