This paper presents an ANSI S1.111/3-octave filter-bank chip for binaural hearing aids with two microphones per ear. Binaural multimicrophone systems significantly suppress noise interference and preserve interaural time cues at the cost of significantly higher computational and power requirements than monophonic single-microphone systems. With clock rates around the 1 MHz mark, these systems are ideal candidates for low-power implementation through charge-recovery design. At such low clock frequencies, however, charge-recovery logic suffers from short-circuit currents that limit its theoretical energy efficiency [1]. The chip described in this paper is designed in 65nm CMOS using a new charge-recovery logic, called zero-short-circuit-current (ZSCC) logic, that drastically reduces short-circuit current. It processes 4 input streams at 1.75MHz with a charge recovery rate of 92%, achieving 9.7× lower power per input compared with the 40nm monophonic single-input chip that represents the published state of the art [2].
Abstract:
This paper presents an ANSI S1.11 1/3-octave filter-bank chip for binaural hearing aids with two microphones per ear. Binaural multimicrophone systems significantly suppr...Show MoreMetadata
Abstract:
This paper presents an ANSI S1.11 1/3-octave filter-bank chip for binaural hearing aids with two microphones per ear. Binaural multimicrophone systems significantly suppress noise interference and preserve interaural time cues at the cost of significantly higher computational and power requirements than monophonic single-microphone systems. With clock rates around the 1MHz mark, these systems are ideal candidates for low-power implementation through charge-recovery design. At such low clock frequencies, however, charge-recovery logic suffers from short-circuit currents that limit its theoretical energy efficiency [1]. The chip described in this paper is designed in 65nm CMOS using a new charge-recovery logic, called zero-short-circuit-current (ZSCC) logic, that drastically reduces short-circuit current. It processes 4 input streams at 1.75MHz with a charge recovery rate of 92%, achieving 9.7× lower power per input compared with the 40nm monophonic single-input chip that represents the published state of the art [2].
Date of Conference: 05-09 February 2017
Date Added to IEEE Xplore: 06 March 2017
ISBN Information:
Electronic ISSN: 2376-8606
29.7 A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS
Chi-Hsiang Huang,Xun Sun,Yidong Chen,Rajesh Pamula,Arindam Mandal,Visvesh Sathe
Single-inductor four-phase power-clock generator for positive-feedback adiabatic logic gates
A. Blotti,S. Borghese,R. Saletti
Design and Implementation of Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids
Yu-Ting Kuo,Tay-Jyi Lin,Yueh-Tai Li,Chih-Wei Liu
A 16-Channel Low-Power Nonuniform Spaced Filter Bank Core for Digital Hearing Aids
K.-S. Chong,B.-H. Gwee,J.S. Chang
Modified LMS-Based Feedback-Reduction Subsystems in Digital Hearing Aids Based on WOLA Filter Bank
RaÚl Vicen-Bueno,Almudena Martinez-Leira,Roberto Gil-Pita,Manuel Rosa-Zurera
10-ms 18-Band Quasi-ANSI S1.11 1/3-Octave Filter Bank for Digital Hearing Aids
Chih-Wei Liu,Kuo-Chiang Chang,Ming-Hsun Chuang,Ching-Hao Lin
Dynamic Frequency Scaling Aware Opportunistic Through-Silicon-Via Inductor Utilization in Resonant Clocking
Umamaheswara Rao Tida,Cheng Zhuo,Leibo Liu,Yiyu Shi
Adjustable Filter Bank Design for Hearing Aids System
Tong Ma,Changpeng Shen,Ying Wei
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control
Chi-Hsiang Huang,Yidong Chen,Xun Sun,Arindam Mandal,Venkata Rajesh Pamula,Nasser Kurd,Visvesh S. Sathe