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Marios Papaefthymiou - IEEE Xplore Author Profile
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Marios Papaefthymiou

Also published under: Marios C. Papaefthymiou, M. C. Papaefthymiou, M. Papaefthymiou, Marlos C. Papaefthymiou

Publications
89
Citations
1,311
Publications by Year
19932023
Co-Authors:
Show All Co-Authors (59)
Image of author Marios Papaefthymiou

Marios Papaefthymiou

Also published under: Marios C. Papaefthymiou, M. C. Papaefthymiou, M. Papaefthymiou, Marlos C. Papaefthymiou

Affiliation

Department of Computer Science
School of Information and Computer Sciences
University of California, Irvine, USA

Publication Topics

Biography

Marios Papaefthymiou is a professor in the Department of Electrical Engineering and Computer Science and Chair of Computer Science and Engineering at the University of Michigan. He is also a cofounder and chief scientist of Cyclos Semiconductor, a start-up company specializing in energy-efficient chips for power-critical applications. Papaefthymiou has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology.(Based on document published on 11 April 2013).
Publications
89
Citations
1,311
Publications by Year
19932023
Co-Authors:
Show All Co-Authors (59)
Author's Published Works

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An Electrical Load Forecasting Method Using An Improved Online Training Strategy

Xinlin Wang;Haizhen Jin;Marios Papaefthymiou

2023 IEEE International Conference on Energy Technologies for Future Grids (ETFG)
Year: 2023 | Conference Paper |
This work proposes a one-step-ahead electrical load forecasting strategy based on machine learning. The approach relies on a novel data-efficient online training data selection mechanism that uses an improved dynamic time warping method to dynamically subselect the most relevant training data from the entire dataset. It also uses an adaptive prediction result optimization method to further enhance...Show More

An Electrical Load Forecasting Method Using An Improved Online Training Strategy

Xinlin Wang;Haizhen Jin;Marios Papaefthymiou

Year: 2023 | Conference Paper |

A Dual-mode Real-time Electrical Load Forecasting Framework

Xinlin Wang;Marios Papaefthymiou

2022 IEEE Power & Energy Society Innovative Smart Grid Technologies Conference (ISGT)
Year: 2022 | Conference Paper |
Cited by: Papers (5)
This paper proposes a real-time electrical load forecasting framework that supports two prediction modes: one-step-ahead and one-day-ahead. The one-step-ahead predictor relies on a feedback mechanism to reduce the impact of random electrical load activity on prediction results. A prediction evaluator assesses previous prediction outcomes to automatically determine the most suitable of the two fore...Show More

A Dual-mode Real-time Electrical Load Forecasting Framework

Xinlin Wang;Marios Papaefthymiou

Year: 2022 | Conference Paper |

A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks

Hsi-Shou Wu;Zhengya Zhang;Marios Papaefthymiou

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)
Year: 2018 | Conference Paper |
Cited by: Papers (2)
A deep-learning processor is presented for achieving ultra-low-power operation in mobile applications. Using a heterogeneous architecture that includes a low-power always-on front-end and a selectively-enabled high-performance backend, the processor dynamically adjusts computational resources at runtime to support conditional execution in neural networks and meet performance targets with increased...Show More

A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks

Hsi-Shou Wu;Zhengya Zhang;Marios Papaefthymiou

Year: 2018 | Conference Paper |

A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices

Shengshuo Lu;Zhengya Zhang;Marios Papaefthymiou

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Year: 2017 | Conference Paper |
Cited by: Papers (3)
An AES core designed for low-cost and energy-efficient IoT security applications is fabricated in a 65nm CMOS technology. A novel Dual-Rail Flush Logic (DRFL) with switching-independent power profile is used to yield intrinsic resistance against Differential Power Analysis (DPA) attacks with minimum area and energy consumption. Measurement results show that this 0.048mm2 core achieves energy consu...Show More

A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices

Shengshuo Lu;Zhengya Zhang;Marios Papaefthymiou

Year: 2017 | Conference Paper |

20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS

Hsi-Shou Wu;Zhengya Zhang;Marios C. Papaefthymiou

2017 IEEE International Solid-State Circuits Conference (ISSCC)
Year: 2017 | Conference Paper |
Cited by: Papers (3)
This paper presents an ANSI S1.11 1/3-octave filter-bank chip for binaural hearing aids with two microphones per ear. Binaural multimicrophone systems significantly suppress noise interference and preserve interaural time cues at the cost of significantly higher computational and power requirements than monophonic single-microphone systems. With clock rates around the 1MHz mark, these systems are ...Show More

20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS

Hsi-Shou Wu;Zhengya Zhang;Marios C. Papaefthymiou

Year: 2017 | Conference Paper |

A 5.5GHz 0.84TOPS/mm2 neural network engine with stream architecture and resonant clock mesh

Shengshuo Lu;Zhengya Zhang;Marios Papaefthymiou

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Year: 2016 | Conference Paper |
This paper presents an ultra-high-performance neural network engine fabricated in a 65nm CMOS technology. The 0.9mm2 core relies on an energy-efficient resonant clock mesh running at 5.5GHz to achieve 0.76 8-bit TOPS, improving throughput by over 4x, area efficiency by over 8×, and energy-delay-area product by over 1.8× compared to previous state-of-the-art neural network designs. Achieving a char...Show More

A 5.5GHz 0.84TOPS/mm2 neural network engine with stream architecture and resonant clock mesh

Shengshuo Lu;Zhengya Zhang;Marios Papaefthymiou

Year: 2016 | Conference Paper |

Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling

Seyong Ahn;Minseok Kang;Marios C. Papaefthymiou;Taewhan Kim

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year: 2016 | Volume: 35, Issue: 12 | Journal Article |
Cited by: Papers (4)
The portion of clock power in system is rapidly increasing with the continuous increasing of clock frequency and clock resources. Last two decades, a great research attention has been paid to minimizing the clock power. Recently, it is shown that the structure of resonant clock networks is very effective in saving power since it can store electric energy to the inserted inductors rather than dissi...Show More

Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling

Seyong Ahn;Minseok Kang;Marios C. Papaefthymiou;Taewhan Kim

Year: 2016 | Volume: 35, Issue: 12 | Journal Article |

A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors

Tai-Chuan Ou;Zhengya Zhang;Marios C. Papaefthymiou

2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Year: 2015 | Conference Paper |
A 576-bit LDPC decoder is designed using a charge-recovery logic family and in-package inductors. The decoder testchip is fabricated in a 65nm CMOS flip-chip process. Unlike all previously published high-performance charge-recovery chips, which use on-chip inductors to recover charge from parasitic capacitance, this charge-recovery design uses in-package inductors, avoiding the area overheads of o...Show More

A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors

Tai-Chuan Ou;Zhengya Zhang;Marios C. Papaefthymiou

Year: 2015 | Conference Paper |

1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks

Shengshuo Lu;Zhengya Zhang;Marios Papaefthymiou

2015 Symposium on VLSI Circuits (VLSI Circuits)
Year: 2015 | Conference Paper |
Cited by: Papers (29)
A 128-bit Advanced Encryption Standard (AES) core targeted for high-performance security applications is fabricated in a 65nm CMOS technology. A novel charge-recovery logic family, called Bridge Boost Logic (BBL), is introduced in this design to achieve switching-independent energy dissipation for an intrinsic high resistance against Differential Power Analysis (DPA) attacks. Based on measurements...Show More

1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks

Shengshuo Lu;Zhengya Zhang;Marios Papaefthymiou

Year: 2015 | Conference Paper |

Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling

Seyong Ahn;Minseok Kang;Marios C. Papaefthymiou;Taewhan Kim

The 20th Asia and South Pacific Design Automation Conference
Year: 2015 | Conference Paper |
The portion of clock power in system is rapidly increasing with the continuous increasing of clock frequency and clock resources. Last two decades, a great research attention has been paid to minimizing the clock power. Recently, it is shown that the structure of resonant clock networks is very effective in saving power since it can store electric energy to the inserted inductors rather than dissi...Show More

Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling

Seyong Ahn;Minseok Kang;Marios C. Papaefthymiou;Taewhan Kim

Year: 2015 | Conference Paper |

On-chip phase change heat sinks designed for computational sprinting

Lei Shao;Arun Raghavan;Laurel Emurian;Marios C. Papaefthymiou;Thomas F. Wenisch;Milo M. K. Martin;Kevin P. Pipe

2014 Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM)
Year: 2014 | Conference Paper |
Cited by: Papers (23)
Computational sprinting has been proposed to improve responsiveness for the intermittent computational demands of many current and emerging mobile applications by briefly activating reserve cores and/or boosting frequency and voltage to power levels that far exceed the system's sustained cooling capability. In this work, we focus on the thermal consequences of computational sprinting, studying the...Show More

On-chip phase change heat sinks designed for computational sprinting

Lei Shao;Arun Raghavan;Laurel Emurian;Marios C. Papaefthymiou;Thomas F. Wenisch;Milo M. K. Martin;Kevin P. Pipe

Year: 2014 | Conference Paper |

27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder

Tai-Chuan Ou;Zhengya Zhang;Marios C. Papaefthymiou

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
Year: 2014 | Conference Paper |
Cited by: Papers (3) | Patents (1)
This paper presents a 576b LDPC decoder test-chip designed using a charge-recovery logic family. The chip has been fabricated in a 65nm CMOS process and relies on 16 integrated inductors to achieve energy-efficient operation by recovering charge from gate fanouts. When self-oscillating at 821MHz, the chip recovers 51.4% of the energy supplied to it. In terms of device count, this chip is more than...Show More

27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder

Tai-Chuan Ou;Zhengya Zhang;Marios C. Papaefthymiou

Year: 2014 | Conference Paper |

Utilizing Dark Silicon to Save Energy with Computational Sprinting

Arun Raghavan;Laurel Emurian;Lei Shao;Marios Papaefthymiou;Kevin P. Pipe;Thomas F. Wenisch;Milo M. K. Martin

IEEE Micro
Year: 2013 | Volume: 33, Issue: 5 | Magazine Article |
Cited by: Papers (31)
Computational sprinting activates dark silicon to improve responsiveness by briefly but intensely exceeding a system's sustainable power limit. This article focuses on the energy implications of sprinting. The authors observe that sprinting can save energy even while improving responsiveness by enabling execution in chip configurations that, though thermally unsustainable, improve energy efficienc...Show More

Utilizing Dark Silicon to Save Energy with Computational Sprinting

Arun Raghavan;Laurel Emurian;Lei Shao;Marios Papaefthymiou;Kevin P. Pipe;Thomas F. Wenisch;Milo M. K. Martin

Year: 2013 | Volume: 33, Issue: 5 | Magazine Article |

Designing for Responsiveness with Computational Sprinting

Arun Raghavan;Yixin Luo;Anuj Chandawalla;Marios Papaefthymiou;Kevin P. Pipe;Thomas F. Wenisch;Milo M.K. Martin

IEEE Micro
Year: 2013 | Volume: 33, Issue: 3 | Magazine Article |
The tight thermal constraints of mobile devices, which limit sustainable performance, and the bursty nature of interactive mobile applications call for a new design focus: enhancing user responsiveness rather than sustained throughput. To that end, this article explores computational sprinting, wherein a mobile device temporarily exceeds sustainable thermal limits to provide a brief, intense burst...Show More

Designing for Responsiveness with Computational Sprinting

Arun Raghavan;Yixin Luo;Anuj Chandawalla;Marios Papaefthymiou;Kevin P. Pipe;Thomas F. Wenisch;Milo M.K. Martin

Year: 2013 | Volume: 33, Issue: 3 | Magazine Article |

Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor

Visvesh S. Sathe;Srikanth Arekapudi;Alexander Ishii;Charles Ouyang;Marios C. Papaefthymiou;Samuel Naffziger

IEEE Journal of Solid-State Circuits
Year: 2013 | Volume: 48, Issue: 1 | Journal Article |
AMD's 32-nm x86-64 core code-named “Piledriver” features a resonant global clock distribution to reduce clock distribution power while maintaining a low clock skew. To support a wide range of operating frequencies expected of the core, the global clock system operates in two modes: a resonant-clock (rclk) mode for energy-efficient operation over a desired frequency range and a conventional, direct...Show More

Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor

Visvesh S. Sathe;Srikanth Arekapudi;Alexander Ishii;Charles Ouyang;Marios C. Papaefthymiou;Samuel Naffziger

Year: 2013 | Volume: 48, Issue: 1 | Journal Article |

Resonant clock design for a power-efficient high-volume x86–64 microprocessor

Visvesh Sathe;Srikanth Arekapudi;Charles Ouyang;Marios Papaefthymiou;Alexander Ishii;Samuel Naffziger

2012 IEEE International Solid-State Circuits Conference
Year: 2012 | Conference Paper |
AMD's 4+ GHz x86-64 core codenamed “Piledriver” employs resonant clocking to reduce clock distribution power up to 24% while maintaining a low clock-skew target. To support testability and robust operation at the wide range of operating frequencies required of a commercial processor, the clock system operates in two modes: direct-drive (cclk) and resonant (rclk). Leveraging favorable factors such ...Show More

Resonant clock design for a power-efficient high-volume x86–64 microprocessor

Visvesh Sathe;Srikanth Arekapudi;Charles Ouyang;Marios Papaefthymiou;Alexander Ishii;Samuel Naffziger

Year: 2012 | Conference Paper |

Computational sprinting

Arun Raghavan;Yixin Luo;Anuj Chandawalla;Marios Papaefthymiou;Kevin P. Pipe;Thomas F. Wenisch;Milo M. K. Martin

IEEE International Symposium on High-Performance Comp Architecture
Year: 2012 | Conference Paper |
Although transistor density continues to increase, voltage scaling has stalled and thus power density is increasing each technology generation. Particularly in mobile devices, which have limited cooling options, these trends lead to a utilization wall in which sustained chip performance is limited primarily by power rather than area. However, many mobile applications do not demand sustained perfor...Show More

Computational sprinting

Arun Raghavan;Yixin Luo;Anuj Chandawalla;Marios Papaefthymiou;Kevin P. Pipe;Thomas F. Wenisch;Milo M. K. Martin

Year: 2012 | Conference Paper |

Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic

Jerry C. Kao;Wei-Hsiang Ma;Visvesh S. Sathe;Marios Papaefthymiou

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year: 2012 | Volume: 20, Issue: 6 | Journal Article |
Cited by: Papers (14)
This paper presents a 14-tap 8-bit finite impulse response (FIR) test-chip that has been designed using a novel charge-recovery logic family, called Enhanced Boost Logic (EBL), to achieve high-speed and low-power operation. Compared to previous charge-recovery circuitry, EBL achieves increased gate overdrive, resulting in low latency overhead over static CMOS design. The EBL-based FIR has been des...Show More

Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic

Jerry C. Kao;Wei-Hsiang Ma;Visvesh S. Sathe;Marios Papaefthymiou

Year: 2012 | Volume: 20, Issue: 6 | Journal Article |

A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution

Wei-Hsiang Ma;Jerry C. Kao;Marios Papaefthymiou

2011 Proceedings of the ESSCIRC (ESSCIRC)
Year: 2011 | Conference Paper |
Cited by: Papers (4)
A 65nm CMOS 5.5GS/s non-interleaved 5-bit flash ADC with resonant clocking is presented. An on-chip 0.77nH inductor resonates the entire clock distribution network to achieve energy-efficient operation. The ADC occupies 0.035mm2 and consumes 28mW when operating at 5.5GHz, yielding 396fJ per conversion step. The clock network dissipates only 10.7% of total power, consuming 54% lower energy over CV2...Show More

A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution

Wei-Hsiang Ma;Jerry C. Kao;Marios Papaefthymiou

Year: 2011 | Conference Paper |

2.07 GHz floating-point unit with resonant-clock precharge logic

C. Kao Jerry;Wei-Hsiang Ma;Suhwan Kim;Marios Papaefthymiou

2010 IEEE Asian Solid-State Circuits Conference
Year: 2010 | Conference Paper |
Cited by: Papers (6)
This paper presents an 8-cycle 64 FO4 single-precision fused-multiply-add floating-point unit (FPU) chip with fine-grain resonant clocking and dynamic-evaluation static-latch logic to achieve dynamic-logic levels performance with significant power reduction. Fabricated in a 90nm low-power RVT technology, the resonant FPU achieves clock speeds up to 2.07GHz. At its resonant frequency of 1.81GHz, it...Show More

2.07 GHz floating-point unit with resonant-clock precharge logic

C. Kao Jerry;Wei-Hsiang Ma;Suhwan Kim;Marios Papaefthymiou

Year: 2010 | Conference Paper |

187 MHz Subthreshold-Supply Charge-Recovery FIR

Wei-Hsiang Ma;Jerry C. Kao;Visvesh S. Sathe;Marios C. Papaefthymiou

IEEE Journal of Solid-State Circuits
Year: 2010 | Volume: 45, Issue: 4 | Journal Article |
Cited by: Papers (27)
This paper presents a finite impulse response (FIR) filter chip that relies on a charge-recovery logic family to achieve multi-MHz clock frequencies with subthreshold DC supply levels. Fabricated in a 0.13 ¿m CMOS process with Vth,nmos = 0.40 V, the FIR operates with a two-phase power-clock in the 5 MHz-187 MHz range and with DC supplies in the 0.16 V-0.36 V range. Using a single DC supply, the ch...Show More

187 MHz Subthreshold-Supply Charge-Recovery FIR

Wei-Hsiang Ma;Jerry C. Kao;Visvesh S. Sathe;Marios C. Papaefthymiou

Year: 2010 | Volume: 45, Issue: 4 | Journal Article |

A resonant-clock 200MHz ARM926EJ-STM microcontroller

Alexander T. Ishii;Jerry C. Kao;Visvesh S. Sathe;Marios C. Papaefthymiou

2009 Proceedings of ESSCIRC
Year: 2009 | Conference Paper |
Cited by: Papers (6)
An ARM926EJ-STM microcontroller with a fully resonant clock distribution network and 16KB data and instruction caches has been implemented in 130nm bulk silicon. Workloads execute successfully across process and temperature corners, and at room temperature, typical-process chips run at clock speeds up to 200MHz with 1.2V supply. At resonance, the microcontroller core dissipates 0.23mW/MHz, recover...Show More

A resonant-clock 200MHz ARM926EJ-STM microcontroller

Alexander T. Ishii;Jerry C. Kao;Visvesh S. Sathe;Marios C. Papaefthymiou

Year: 2009 | Conference Paper |

A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead

Jerry C. Kao;Wei-Hsiang Ma;Visvesh S. Sathe;Marios Papaefthymiou

2009 Proceedings of ESSCIRC
Year: 2009 | Conference Paper |
Cited by: Papers (5)
We present a 14-tap 8-bit FIR chip designed using a novel charge-recovery logic family with only 1.5 cycles of additional latency over the best possible static CMOS design. Fabricated in a 0.13 mum CMOS process, the chip operates in the 365-600 MHz range with a 3 nH on-chip inductor. At its resonant frequency of 466 MHz, it dissipates 39.1 mW and recovers 45% of the energy supplied to it.Show More

A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead

Jerry C. Kao;Wei-Hsiang Ma;Visvesh S. Sathe;Marios Papaefthymiou

Year: 2009 | Conference Paper |

A 187MHz subthreshold-supply robust FIR filter with charge-recovery logic

Wei-Hsiang Ma;Jerry C. Kao;Visvesh S. Sathe;Marios Papaefthymiou

2009 Symposium on VLSI Circuits
Year: 2009 | Conference Paper |
Cited by: Papers (6)
A 187MHz FIR filter with a single subthreshold DC supply is designed using a charge-recovery logic family. Fabricated in a 0.13µm CMOS process with Vth,nmos = 0.40V, the FIR operates in the 80MHz–187MHz range with DC supply in the 0.30V–0.36V range, respectively. Resonating at 100MHz, it consumes 21.27pJ per cycle and achieves 23.7nW/Tap/MHz/InBit/CoeffBit.Show More

A 187MHz subthreshold-supply robust FIR filter with charge-recovery logic

Wei-Hsiang Ma;Jerry C. Kao;Visvesh S. Sathe;Marios Papaefthymiou

Year: 2009 | Conference Paper |

Resonant-Clock Latch-Based Design

Visvesh S. Sathe;Jerry C. Kao;Marios C. Papaefthymiou

IEEE Journal of Solid-State Circuits
Year: 2008 | Volume: 43, Issue: 4 | Journal Article |
This paper describes RF1 and RF2, two level-clocked test-chips that deploy resonant clocking to reduce power consumption in their clock distribution networks. It also highlights RCL, a novel resonant-clock latch-based methodology that was used to design the two test-chips. RF1 and RF2 are 8-bit 14-tap finite-impulse response (FIR) filters with identical architectures. Designed using a fully automa...Show More

Resonant-Clock Latch-Based Design

Visvesh S. Sathe;Jerry C. Kao;Marios C. Papaefthymiou

Year: 2008 | Volume: 43, Issue: 4 | Journal Article |

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