Contents This paper presents an ANSI S1.111/3-octave filter-bank chip for binaural hearing aids with two microphones per ear. Binaural multimicrophone systems significantly suppress noise interference and preserve interaural time cues at the cost of significantly higher computational and power requirements than monophonic single-microphone systems. With clock rates around the 1 MHz mark, these systems are ideal candidates for low-power implementation through charge-recovery design. At such low clock frequencies, however, charge-recovery logic suffers from short-circuit currents that limit its theoretical energy efficiency [1]. The chip described in this paper is designed in 65nm CMOS using a new charge-recovery logic, called zero-short-circuit-current (ZSCC) logic, that drastically reduces short-circuit current. It processes 4 input streams at 1.75MHz with a charge recovery rate of 92%, achieving 9.7× lower power per input compared with the 40nm monophonic single-input chip that represents the published state of the art [2].
Abstract:
This paper presents an ANSI S1.11 1/3-octave filter-bank chip for binaural hearing aids with two microphones per ear. Binaural multimicrophone systems significantly suppr...Show MoreMetadata
Abstract:
This paper presents an ANSI S1.11 1/3-octave filter-bank chip for binaural hearing aids with two microphones per ear. Binaural multimicrophone systems significantly suppress noise interference and preserve interaural time cues at the cost of significantly higher computational and power requirements than monophonic single-microphone systems. With clock rates around the 1MHz mark, these systems are ideal candidates for low-power implementation through charge-recovery design. At such low clock frequencies, however, charge-recovery logic suffers from short-circuit currents that limit its theoretical energy efficiency [1]. The chip described in this paper is designed in 65nm CMOS using a new charge-recovery logic, called zero-short-circuit-current (ZSCC) logic, that drastically reduces short-circuit current. It processes 4 input streams at 1.75MHz with a charge recovery rate of 92%, achieving 9.7× lower power per input compared with the 40nm monophonic single-input chip that represents the published state of the art [2].
Date of Conference: 05-09 February 2017
Date Added to IEEE Xplore: 06 March 2017
ISBN Information:
Electronic ISSN: 2376-8606
Citations are not available for this document.
Cites in Papers - |
Cites in Papers - IEEE (2)
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1.
Bo Liu, Xuetao Wang, Renyuan Zhang, Anfeng Xue, Ziyu Wang, Haige Wu, Hao Cai, "A Low Power DNN-based Speech Recognition Processor with Precision Recoverable Approximate Computing", 2022 IEEE International Symposium on Circuits and Systems (ISCAS), pp.2102-2106, 2022.
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Bo Liu, Hao Cai, Yu Gong, Wentao Zhu, Yan Li, Wei Ge, Zhen Wang, "Binarized Weight Neural-Network Inspired Ultra-Low Power Speech Recognition Processor with Time-Domain Based Digital-Analog Mixed Approximate Computing", 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-5, 2020.
Cites in Papers - Other Publishers (1)
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Atryee Bhuyan, Manash Pratim Sarma, Nikos E Mastorakis, "Design and Implementation of an Area and Power-efficient Reconfigurable Hearing Aid using Interpolated Sub-band Distribution Technique", WSEAS TRANSACTIONS ON SYSTEMS, vol.21, pp.312, 2022.
