29.7 A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS | IEEE Conference Publication | IEEE Xplore

29.7 A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS


Abstract:

Single-inductor multiple-output (SIMO) converters present a promising technology for enabling fine-grained supply-voltage (Vdd) domains in SoCs. With efficiencies approac...Show More

Abstract:

Single-inductor multiple-output (SIMO) converters present a promising technology for enabling fine-grained supply-voltage (Vdd) domains in SoCs. With efficiencies approaching those of buck converters, SIMO converters allow multiple domains to share a single inductor, thus reducing the use of bulky passive components [1-5]. However, SIMO converters suffer from a poor transient response and significant ripple, requiring extensive Vdd margining. Operation at an elevated Vdd-and, therefore, the load-current (Iload )-inflates power draw and further reduces system efficiency (ηsystem), i.e. the ratio of the useful (margin-free) output power to input power draw.
Date of Conference: 13-22 February 2021
Date Added to IEEE Xplore: 03 March 2021
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ISSN Information:

Conference Location: San Francisco, CA, USA

Single-inductor multiple-output (SIMO) converters present a promising technology for enabling fine-grained supply-voltage domains in SoCs. With efficiencies approaching those of buck converters, SIMO converters allow multiple domains to share a single inductor, thus reducing the use of bulky passive components [1–5]. However, SIMO converters suffer from a poor transient response and significant ripple, requiring extensive margining. Operation at an elevated -and, therefore, the load-current - inflates power draw and further reduces system efficiency , i.e. the ratio of the useful (margin-free) output power to input power draw.

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