Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link

Differential signaling has been widely used in high-speed interconnects. Signal integrity issues, such as inter-symbol interference (ISI) and crosstalk between the differential pair, however, still cause significant timing jitter and amplitude noise and heavily limit the performance of the differential link. The pre-emphasis filter is commonly used to reduce ISI but may potentially change the crosstalk behavior. In this paper, we first propose formula-based jitter and noise models considering the combined effect of ISI, crosstalk, and pre-emphasis filter. With the same set of input patterns, experiment shows our models achieve within 5% difference compared with SPICE simulation. By utilizing these formula-based models, we then develop algorithms to directly find out the input patterns for worst-case jitter and worst-case amplitude noise through pseudo-Boolean optimization (PBO) and mathematical programming. In addition, a heuristic algorithm is proposed to further reduce runtime. Experiments show our algorithms obtain more reliable worst-case jitter and noise compared with pseudorandom bit sequences simulation and, meanwhile, reduce runtime by 25× when using a general PBO solver and by 150× when using our proposed heuristic algorithm.

I. Introduction

Differential signaling has been widely used in high-speed I/O interconnect standards like PCI-Express and Serial ATA. It has several advantages, such as a high transmission rate due to low signal swing, little electromagnetic interference (EMI), and common-mode noise immunity. Considerable signal integrity issues, however, still limit the link performance and become bottlenecks during system integration. Such issues include resistive losses, reflections, inductive ringing and crosstalk between differential pairs [2], [3].