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Sudhakar Pamarti - IEEE Xplore Author Profile

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Author details

Sudhakar Pamarti

Also published under: S. Pamarti, Sudhkar Pamarti

Publications

118

Citations

1,594

Publications by Year

20032025

Co-Authors:

Bipul AgarwalIrina AlamE. AlonAbdulaziz AlshayaCarl Arft

Show All Co-Authors (165)

Sudhakar Pamarti

Also published under: S. Pamarti, Sudhkar Pamarti

Affiliation

Department of Electrical and Computer Engineering

University of California at Los Angeles (UCLA)

Los Angeles, CA, USA

Publication Topics

Analog-to-digital Converter,
Digital Circuits,
Noise Floor,
Analog Circuits,
Bitstream,
Deep Learning,
Digital Cancellation,
Digital Domain,
Digital Techniques,
Digital Technologies,
Dot Product,
Energy Conservation

Biography

Sudhakar Pamarti (S'98–M'03) received the B.Tech. degree in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur, India, in 1995, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, San Diego, CA, USA, in 1999 and 2003, respectively.,He is an Associate Professor of electrical engineering at the University of California, Los Angeles (UCLA), CA, USA. Prior to joining UCLA, he worked at Rambus Inc. (2003–2005) and Hughes Software Systems (1995–1997) developing high-speed I/O circuits and embedded software and firmware for a wireless-in-local-loop communication system, respectively.,Dr. Pamarti was a recipient of the National Science Foundation's CAREER a...

Publications

118

Citations

1,594

Publications by Year

20032025

Co-Authors:

Bipul Agarwal
Irina Alam
E. Alon
Abdulaziz Alshaya
Carl Arft

Show All Co-Authors (165)

Author's Published Works

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Showing 1-25 of 118 results

Conferences (65)

Journals (52)

Magazines (1)

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Sudhakar Pamarti(110)
Puneet Gupta(15)
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Department of Electrical Engineering, University of California, Los Angeles, CA, USA(15)
University of California, Los Angeles, CA(11)
Electrical Engineering Department, University of California, Los Angeles, CA, USA(9)
University of California, Los Angeles, CA, USA(6)
Department of Electrical and Computer Engineering, University of California, Los Angeles, CA, USA(6)
IEEE Journal of Solid-State Circuits(21)
IEEE Transactions on Circuits and Systems I: Regular Papers(9)
IEEE Transactions on Circuits and Systems II: Express Briefs(6)
IEEE Transactions on Microwave Theory and Techniques(4)
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)(3)
IEEE(118)
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San Francisco, CA, USA(13)
Austin, TX, USA(5)
Grenoble, France(5)
San Jose, CA, USA(4)
Kyoto, Japan(3)
Quantization Noise(28)
Analog-to-digital Converter(24)
Phase Noise(22)
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A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation

Zhichao Chen;Ali H. Hassan;Rhesa Ramadhan;Yingheng Li;Chih-Kong Ken Yang;Sudhakar Pamarti;Puneet Gupta

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2025 | Volume: 33, Issue: 1 | Journal Article |

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Low-temperature (LT) conditions can potentially lead to lower power consumption and enhanced performance in circuit operations by reducing the transistor leakage current, increasing carrier mobility, reducing wear-out, and reducing interconnect resistance. We develop PROCEED-LT, a pathfinding framework to co-optimize devices and circuits over a wide performance range. Our results demonstrate that ...Show More

A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation

Zhichao Chen;Ali H. Hassan;Rhesa Ramadhan;Yingheng Li;Chih-Kong Ken Yang;Sudhakar Pamarti;Puneet Gupta

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2025 | Volume: 33, Issue: 1 | Journal Article |

Cryogenic Alternative: CMOS Versus Dynamic-Based Logic

Ali H. Hassan;Puneet Gupta;Sudhakar Pamarti;Chih-Kong Ken Yang

2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS)

Year: 2024 | Conference Paper |

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Next-generation data-center computing requires high-performance energy-efficient servers. One counterintuitive approach to reduce energy is to lower the temperature of the processing elements even down to cryogenic temperatures of liquid nitrogen. If the processing load is reduced dramatically, the net energy cost is lower even considering the corresponding cooling cost. Operating at such temperat...Show More

Cryogenic Alternative: CMOS Versus Dynamic-Based Logic

Ali H. Hassan;Puneet Gupta;Sudhakar Pamarti;Chih-Kong Ken Yang

2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS)

Year: 2024 | Conference Paper |

SCIMITAR: Stochastic Computing In-Memory In-Situ Tracking ARchitecture for Event-Based Cameras

Wojciech Romaszkan;Jiyue Yang;Alexander Graening;Vinod K. Jacob;Jishnu Sen;Sudhakar Pamarti;Puneet Gupta

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2024 | Volume: 43, Issue: 11 | Journal Article |

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Event-based cameras offer low latency and high-dynamic range imaging data in a sparse format that is well-suited for high-speed object tracking. Processing this sparse data in the same way as traditional camera data requires a great deal of unnecessary computation, making it difficult to take advantage of the high-effective frame rate for real-time processing. In this work, we propose an accelerat...Show More

SCIMITAR: Stochastic Computing In-Memory In-Situ Tracking ARchitecture for Event-Based Cameras

Wojciech Romaszkan;Jiyue Yang;Alexander Graening;Vinod K. Jacob;Jishnu Sen;Sudhakar Pamarti;Puneet Gupta

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2024 | Volume: 43, Issue: 11 | Journal Article |

Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <–103-dBc Spurious Tones Using Digital Spur Cancellation

Mohammadreza Zeinali;Szu-Yao Hung;Sudhakar Pamarti

IEEE Journal of Solid-State Circuits

Year: 2024 | Volume: 59, Issue: 10 | Journal Article |

Cited by: Papers (1)

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In this article, we describe an advanced multi-output fractional frequency synthesizer (FFS) featuring an innovative digital spur cancellation technique. This technique not only effectively suppresses fractional- $N$ spurs but also eliminates externally coupled spurious tones. In addition, this article includes a comprehensive exploration of the proposed method, offering theoretical analysis and ...Show More

Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <–103-dBc Spurious Tones Using Digital Spur Cancellation

Mohammadreza Zeinali;Szu-Yao Hung;Sudhakar Pamarti

IEEE Journal of Solid-State Circuits

Year: 2024 | Volume: 59, Issue: 10 | Journal Article |

Digital Residual Alias Cancellation for Filtering-by-Aliasing Receivers

Shi Bu;Vinod Kurian Jacob;Sudhakar Pamarti

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2024 | Volume: 71, Issue: 4 | Journal Article |

Cited by: Papers (1)

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The filtering-by-aliasing (FA) receivers have demonstrated sharp analog finite impulse response (FIR) filtering by combining periodically time-varying (PTV) circuit elements with uniform sampling. Seen at the sampled output, the impulse response of an FA receiver can be controlled by the PTV resistor’s resistance that varies over time, which realizes very sharp filtering with 50–70-dB stopband rej...Show More

Digital Residual Alias Cancellation for Filtering-by-Aliasing Receivers

Shi Bu;Vinod Kurian Jacob;Sudhakar Pamarti

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2024 | Volume: 71, Issue: 4 | Journal Article |

FPGA Crystal Oscillator Circuit Emulation Based on Wave Digital Filter

Abdulaziz Alshaya;Sudhakar Pamarti;Christos Papavassiliou

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2024 | Volume: 32, Issue: 1 | Journal Article |

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The design cycle of analog and mixed signal (AMS) components requires the designer to iteratively perform analog simulations, layout, fabrication, and hardware testing. Unlike digital designs, system verification is a difficult task in analog designs, primarily due to a lack of emulation. Thus, a method to emulate AMS components on digital hardware would be highly beneficial. In this work, a high-...Show More

FPGA Crystal Oscillator Circuit Emulation Based on Wave Digital Filter

Abdulaziz Alshaya;Sudhakar Pamarti;Christos Papavassiliou

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2024 | Volume: 32, Issue: 1 | Journal Article |

A Spur-free Dynamic Element Matching Scheme for Bandpass DACs

Jarrah Bergeron;Sudhakar Pamarti

2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)

Year: 2023 | Conference Paper |

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Dynamic element matching (DEM) is a popular class of techniques that exploit redundancy to linearize digital-to-analog converters (DACs) in the presence of component mismatches. Most DEM techniques employ spectral shaping of the DAC mismatch error power, often in conjunction with randomization, to suppress in-band error and spurious tones. However, spurious tone elimination is mathematically guara...Show More

A Spur-free Dynamic Element Matching Scheme for Bandpass DACs

Jarrah Bergeron;Sudhakar Pamarti

2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)

Year: 2023 | Conference Paper |

REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration

Tianmu Li;Wojciech Romaszkan;Sudhakar Pamarti;Puneet Gupta

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2023 | Volume: 42, Issue: 12 | Journal Article |

Cited by: Papers (3)

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Deep learning has grown in capability and size in recent years, prompting research on alternative computing methods to cope with the increased compute cost. Stochastic computing (SC) promises higher compute efficiency with its compact compute units, but accuracy issues have prevented wide adoption, and accuracy-improving techniques have sacrificed runtime or training performance. In this work, we ...Show More

REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration

Tianmu Li;Wojciech Romaszkan;Sudhakar Pamarti;Puneet Gupta

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2023 | Volume: 42, Issue: 12 | Journal Article |

A Nonvolatile Compute-in-Memory Macro Using Voltage-Controlled MRAM and In Situ Magnetic-to-Digital Converter

Vinod Kurian Jacob;Jiyue Yang;Haoran He;Puneet Gupta;Kang L Wang;Sudhakar Pamarti

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

Year: 2023 | Volume: 9, Issue: 1 | Journal Article |

Cited by: Papers (4)

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Compute-in-memory (CIM) accelerator has become a popular solution to achieve high energy efficiency for deep learning applications in edge devices. Recent works have demonstrated CIM macros using nonvolatile memories [spin transfer torque (STT)-MRAM and resistive random access memory (RRAM)] to take advantages of their nonvolatility and high density. However, effective computation dynamic range is...Show More

A Nonvolatile Compute-in-Memory Macro Using Voltage-Controlled MRAM and In Situ Magnetic-to-Digital Converter

Vinod Kurian Jacob;Jiyue Yang;Haoran He;Puneet Gupta;Kang L Wang;Sudhakar Pamarti

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

Year: 2023 | Volume: 9, Issue: 1 | Journal Article |

A Low Power 100 GHz Static CML Frequency Divider in 0.18 μm SiGe BiCMOS Technology

Hao-Yu Chien;Christopher Chen;Jason Woo;Sudhakar Pamarti;Chih-Kong Ken Yang;Mau-Chung Frank Chang

2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

Year: 2023 | Conference Paper |

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A100 GHz wideband static divider is implemented on a 0. 1S$\mu$mSiGe BiCMOS technology. The divider achieves a self-resonant frequency (SRF) of 92.5 GHz with a maximum dividing frequency of 100 GHz. The required input power is less than 0dBm across the entire operating range. The divider consumes 66 mW. The circuit has a 100 x SO $\mu \mathrm{m}^{2}$ active areaShow More

A Low Power 100 GHz Static CML Frequency Divider in 0.18 μm SiGe BiCMOS Technology

Hao-Yu Chien;Christopher Chen;Jason Woo;Sudhakar Pamarti;Chih-Kong Ken Yang;Mau-Chung Frank Chang

2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

Year: 2023 | Conference Paper |

Low-Energy Shared-Current Write Schemes for Voltage-Controlled Spin-Orbit-Torque Memory

Albert Lee;Irina Alam;Jiyue Yang;Di Wu;Sudhakar Pamarti;Puneet Gupta;Kang L. Wang

IEEE Transactions on Electron Devices

Year: 2023 | Volume: 70, Issue: 2 | Journal Article |

Cited by: Papers (4)

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Voltage-controlled (VC) spin-orbit-torque (SOT) magnetic random access memory (MRAM) is being considered as the next-generation magnetic memory with potential to achieve superior speed, power, and write error rates over existing MRAM technologies. By placing multiple VC devices on a single SOT bus, VC-SOT MRAM can also enable compact structures, in which multiple devices can be addressed individua...Show More

Low-Energy Shared-Current Write Schemes for Voltage-Controlled Spin-Orbit-Torque Memory

Albert Lee;Irina Alam;Jiyue Yang;Di Wu;Sudhakar Pamarti;Puneet Gupta;Kang L. Wang

IEEE Transactions on Electron Devices

Year: 2023 | Volume: 70, Issue: 2 | Journal Article |

Demonstration of Analog Compute-In-Memory Using the Charge-Trap Transistor in 22 FDX Technology

S. Qiao;S. Moran;D. Srinivas;S. Pamarti;S. S. Iyer

2022 International Electron Devices Meeting (IEDM)

Year: 2022 | Conference Paper |

Cited by: Papers (2)

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Most analog compute-in-memory (CIM) devices suffer from low on/off ratio, large IR drop, limited retention capability, the need for an additional access device, and additional process complexity for embedding in commercial CMOS logic. To overcome these disadvantages, the charge-trap transistor (CTT) has been proposed. It uses commercial off-the-shelf technology (22 FDX demonstrated in this work) w...Show More

Demonstration of Analog Compute-In-Memory Using the Charge-Trap Transistor in 22 FDX Technology

S. Qiao;S. Moran;D. Srinivas;S. Pamarti;S. S. Iyer

2022 International Electron Devices Meeting (IEDM)

Year: 2022 | Conference Paper |

A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor

Jiyue Yang;Tianmu Li;Wojciech Romaszkan;Puneet Gupta;Sudhakar Pamarti

2022 IEEE Asian Solid-State Circuits Conference (A-SSCC)

Year: 2022 | Conference Paper |

Cited by: Papers (3)

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High compute density improves the data reuse and is the key to reducing off-chip memory access and achieving high energy efficiency in ML accelerators. Compute-in-Memory (CIM) promises high compute density but requires ADCs, DACs that add to the macro’s energy and area [1] [2] limiting its compute density. Besides, CIM’s analog compute is sensitive to process variability and mismatches. The transi...Show More

A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor

Jiyue Yang;Tianmu Li;Wojciech Romaszkan;Puneet Gupta;Sudhakar Pamarti

2022 IEEE Asian Solid-State Circuits Conference (A-SSCC)

Year: 2022 | Conference Paper |

A 14-bit 1-GS/s SiGe Bootstrap Sampler for High Resolution ADC with 250-MHz Input

Jiazhang Song;Li-Yang Chen;Mau-Chung Frank Chang;Sudhakar Pamarti;Chih-Kong Ken Yang

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

Year: 2022 | Conference Paper |

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An 86.6-dB SFDR, 1-GS/s differential bootstrap sampler in a 0.18-um SiGe BiCMOS technology is presented. The performance is achieved using an amplitude-modulated bootstrap circuit. The results show 14-bit linearity over nearly 500-MHz bandwidth, while consuming less power compared to a conventional MOSFET switched-capacitor bootstrap circuit due to less parasitic capacitance and the use of high ft...Show More

A 14-bit 1-GS/s SiGe Bootstrap Sampler for High Resolution ADC with 250-MHz Input

Jiazhang Song;Li-Yang Chen;Mau-Chung Frank Chang;Sudhakar Pamarti;Chih-Kong Ken Yang

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

Year: 2022 | Conference Paper |

A Digital Alias Cancellation Technique for Filtering-by-Aliasing Receivers

Shi Bu;Vinod Kurian Jacob;Sudhakar Pamarti

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

Year: 2022 | Conference Paper |

Cited by: Papers (1)

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There has been a growing trend of developing programmable transceivers, which are the key to realizing a true software-defined radio [1]. Some prior works, such as N-path filters and mixer-first receivers, utilized periodically time-varying (PTV) circuits and have shown some promises and achieved what conventional time-invariant circuits are incapable of. Among them, the filtering-by-aliasing (FA)...Show More

A Digital Alias Cancellation Technique for Filtering-by-Aliasing Receivers

Shi Bu;Vinod Kurian Jacob;Sudhakar Pamarti

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

Year: 2022 | Conference Paper |

A 4.4–75-TOPS/W 14-nm Programmable, Performance- and Precision-Tunable All-Digital Stochastic Computing Neural Network Inference Accelerator

Wojciech Romaszkan;Tianmu Li;Rahul Garg;Jiyue Yang;Sudhakar Pamarti;Puneet Gupta

IEEE Solid-State Circuits Letters

Year: 2022 | Volume: 5 | Journal Article |

Cited by: Papers (5)

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We present the first programmable and precision-tunable stochastic computing (SC) neural network (NN) inference accelerator. The use of SC makes it possible to achieve multiply–accumulate (MAC) density of 38.4k MAC/mm2, enabling a level of spatial data reuse unachievable to conventional, fixed-point architectures. This extensive reuse amortizes the cost of SC conversion and reduces the number of m...Show More

A 4.4–75-TOPS/W 14-nm Programmable, Performance- and Precision-Tunable All-Digital Stochastic Computing Neural Network Inference Accelerator

Wojciech Romaszkan;Tianmu Li;Rahul Garg;Jiyue Yang;Sudhakar Pamarti;Puneet Gupta

IEEE Solid-State Circuits Letters

Year: 2022 | Volume: 5 | Journal Article |

A Dual-Channel High-Linearity Filtering-by-Aliasing Receiver Front-End Supporting Carrier Aggregation

Shi Bu;Sudhakar Pamarti

IEEE Journal of Solid-State Circuits

Year: 2022 | Volume: 57, Issue: 5 | Journal Article |

Cited by: Papers (9)

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A filtering-by-aliasing (FA) receiver front-end based on a slice-based time-varying architecture was described by Bu and Pamarti (2021). Unlike prior FA architectures, it demonstrated, using a 28-nm CMOS prototype IC, a time-invariant input impedance that enables dual-channel operation with high linearity. Up to 50-dB stopband rejection with a transition bandwidth (BW) of only 3.2 times the RF BW,...Show More

A Dual-Channel High-Linearity Filtering-by-Aliasing Receiver Front-End Supporting Carrier Aggregation

Shi Bu;Sudhakar Pamarti

IEEE Journal of Solid-State Circuits

Year: 2022 | Volume: 57, Issue: 5 | Journal Article |

A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM

Jiyue Yang;Di Wu;Albert Lee;Seyed Armin Razavi;Puneet Gupta;Kang L. Wang;Sudhakar Pamarti

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC)

Year: 2021 | Conference Paper |

Cited by: Papers (3)

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In this paper, we propose an in-memory True Random Number Generator (TRNG) using Voltage-Controlled MRAM that doesn't require calibration of the writing pulse's width and amplitude. Previous solution using Spin Transfer Torque (STT) MRAM requires calibration for every MTJ, thus making the multi-row random number generation inside the memory impossible. We also propose a 100% relative throughput di...Show More

A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM

Jiyue Yang;Di Wu;Albert Lee;Seyed Armin Razavi;Puneet Gupta;Kang L. Wang;Sudhakar Pamarti

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC)

Year: 2021 | Conference Paper |

Designing a 2048-Chiplet, 14336-Core Waferscale Processor

Saptadeep Pal;Jingyang Liu;Irina Alam;Nicholas Cebry;Haris Suhail;Shi Bu;Subramanian S. Iyer;Sudhakar Pamarti;Rakesh Kumar;Puneet Gupta

2021 58th ACM/IEEE Design Automation Conference (DAC)

Year: 2021 | Conference Paper |

Cited by: Papers (25)

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Waferscale processor systems can provide the large number of cores, and memory bandwidth required by today’s highly parallel workloads. One approach to building waferscale systems is to use a chiplet-based architecture where pre-tested chiplets are integrated on a passive silicon-interconnect wafer. This technology allows heterogeneous integration and can provide significant performance and cost b...Show More

Designing a 2048-Chiplet, 14336-Core Waferscale Processor

Saptadeep Pal;Jingyang Liu;Irina Alam;Nicholas Cebry;Haris Suhail;Shi Bu;Subramanian S. Iyer;Sudhakar Pamarti;Rakesh Kumar;Puneet Gupta

2021 58th ACM/IEEE Design Automation Conference (DAC)

Year: 2021 | Conference Paper |

A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM

Jiyue Yang;Di Wu;Albert Lee;Seyed Armin Razavi;Puneet Gupta;Kang L. Wang;Sudhakar Pamarti

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)

Year: 2021 | Conference Paper |

Cited by: Papers (3)

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In this paper, we propose an in-memory True Random Number Generator (TRNG) using Voltage-Controlled MRAM that doesn't require calibration of the writing pulse's width and amplitude. Previous solution using Spin Transfer Torque (STT) MRAM requires calibration for every MTJ, thus making the multi-row random number generation inside the memory impossible. We also propose a 100% relative throughput di...Show More

A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM

Jiyue Yang;Di Wu;Albert Lee;Seyed Armin Razavi;Puneet Gupta;Kang L. Wang;Sudhakar Pamarti

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)

Year: 2021 | Conference Paper |

A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS

Yan Zhang;Chia-Jen Liang;Christopher Chen;Andrew Liu;Jason Woo;Sudhakar Pamarti;Chih-Kong Ken Yang;Mau-Chung Frank Chang

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)

Year: 2021 | Conference Paper |

Cited by: Papers (4)

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This paper presents a 27.0-30.5 GHz sub-sampling PLL implemented in a 0.18um SiGe BiCMOS process. The PLL incorporates an improved Class-C VCO with a supply-side 2nd-harmonic common-mode resonance and a completely floating, transformer-based 3rd-harmonic differential-mode resonance. Despite the limitation of the 0.18µm CMOS devices at high frequencies, the prototype achieves record low in-band noi...Show More

A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS

Yan Zhang;Chia-Jen Liang;Christopher Chen;Andrew Liu;Jason Woo;Sudhakar Pamarti;Chih-Kong Ken Yang;Mau-Chung Frank Chang

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)

Year: 2021 | Conference Paper |

I/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor

Saptadeep Pal;Irina Alam;Krutikesh Sahoo;Haris Suhail;Rakesh Kumar;Sudhakar Pamarti;Puneet Gupta;Subramanian S. Iyer

2021 IEEE 71st Electronic Components and Technology Conference (ECTC)

Year: 2021 | Conference Paper |

Cited by: Papers (4)

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Demand for large amounts of parallelism is growing rapidly for today's computing systems. This is due to the proliferation of applications such as graph processing, data analytics, machine learning, etc. which require a large number of processing cores and a large amount of memory bandwidth. Often systems comprising of many individual packaged chips are employed to run these applications. However,...Show More

I/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor

Saptadeep Pal;Irina Alam;Krutikesh Sahoo;Haris Suhail;Rakesh Kumar;Sudhakar Pamarti;Puneet Gupta;Subramanian S. Iyer

2021 IEEE 71st Electronic Components and Technology Conference (ECTC)

Year: 2021 | Conference Paper |

GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks

Tianmu Li;Wojciech Romaszkan;Sudhakar Pamarti;Puneet Gupta

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Year: 2021 | Conference Paper |

Cited by: Papers (7)

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Stochastic computing (SC) has seen a renaissance in recent years as a means for machine learning acceleration due to its compact arithmetic and approximation properties. Still, SC accuracy remains an issue, with prior works either not fully utilizing the computational density or suffering from significant accuracy losses. In this work, we propose GEO - Generation and Execution Optimized Stochastic...Show More

GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks

Tianmu Li;Wojciech Romaszkan;Sudhakar Pamarti;Puneet Gupta

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Year: 2021 | Conference Paper |

6.3 A 0.9V Dual-Channel Filtering-by-Aliasing Receiver Front-End Achieving +35dBm IIP3 and <-81dBm LO Leakage Supporting Intra-and Inter-Band Carrier Aggregation

Shi Bu;Sudhakar Pamarti

2021 IEEE International Solid-State Circuits Conference (ISSCC)

Year: 2021 | Conference Paper |

Cited by: Papers (1)

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Programmable receivers have drawn a lot of attention in recent years, especially those exploiting periodically time-varying (PTV) circuits. N-path filters and mixer-first receivers [1- 3] achieve sharp filtering and good linearity but can suffer from high LO leakage (> -70 dBm), which is not compliant with the FCC requirements [4]. In addition, they do not support multi-carrier operation very well...Show More

6.3 A 0.9V Dual-Channel Filtering-by-Aliasing Receiver Front-End Achieving +35dBm IIP3 and <-81dBm LO Leakage Supporting Intra-and Inter-Band Carrier Aggregation

Shi Bu;Sudhakar Pamarti

2021 IEEE International Solid-State Circuits Conference (ISSCC)

Year: 2021 | Volume: 64 | Conference Paper |

Periodically Time-Varying Noise Cancellation for Filtering-by-Aliasing Receiver Front Ends

Shi Bu;Sameed Hameed;Sudhakar Pamarti

IEEE Journal of Solid-State Circuits

Year: 2021 | Volume: 56, Issue: 3 | Journal Article |

Cited by: Papers (11)

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This article presents a periodically time-varying (PTV) noise cancellation technique for filtering-by-aliasing (FA) receivers. The key to the proposed technique is the use of a time-varying transconductance (Gm) cell to sense the noise generated by the PTV resistor in an FA receiver while maintaining the sharp filtering offered by FA. A prototype IC fabricated in a 28-nm CMOS process improves the ...Show More

Periodically Time-Varying Noise Cancellation for Filtering-by-Aliasing Receiver Front Ends

Shi Bu;Sameed Hameed;Sudhakar Pamarti

IEEE Journal of Solid-State Circuits

Year: 2021 | Volume: 56, Issue: 3 | Journal Article |

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