STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures

Reducing the energy consumption of parallel applications is becoming increasingly important. Current chip multiprocessors (CMPs) incorporate asymmetric cores (i.e. static asymmetry) and DVFS (i.e. dynamic asymmetry) to enable energy efficient execution. To reduce cost and complexity, designs typically organize asymmetric cores into core-clusters supporting the same DVFS setting across cores in a cluster. Recent approaches that focus on energy efficient scheduling of task-based parallel applications predominantly rely on dynamic asymmetry, particularly per-core DVFS, for reducing energy. More importantly, they do not consider the impact of task heterogeneity (i.e. varying task characteristics, intra-task parallelism and task granularity) in conjunction with the dynamic and static asymmetries provided by the platform. Together, these provide significant opportunities for further energy savings. In this work we propose STEER, a framework that enables energy efficient execution of task-based parallel applications by leveraging static asymmetry, dynamic asymmetry and task heterogeneity. STEER utilizes a combination of models and heuristics to predict the execution time and power consumption and determine core type, number of cores and frequency for running tasks. Our evaluation shows that STEER achieves 38% energy reduction on average compared to the state-of-the-art approaches.

I. Introduction

Reducing energy consumption has become an increasingly important goal as it translates directly into electricity cost savings in data centers and supercomputing centers, and longer battery life in mobile devices. At the CMP level, common techniques to reduce energy include integrating asymmetric cores (i.e. static asymmetry) for efficient execution of different workloads [1], and leveraging DVFS (i.e. dynamic asymmetry) to match the core's performance to the program requirements [2]. However, as core counts increase, scaling DVFS and asymmetry complicate hardware designs. One way to reduce this complexity is by organizing the cores into clusters. This strategy has been used to organize monolithic CMPs [3] and chiplet-based CMP designs [4], [5], and is expected to continue with the trend towards heterogeneous integration [6]. In such designs, all cores in a cluster are of the same type and operate at the same DVFS setting.