Power Delivery for High-Performance Microprocessors—Challenges, Solutions, and Future Trends

The power delivery requirements for the early microprocessors were fairly rudimentary due to the relatively low power levels. However, several decades of exponential scaling powered by Moore's law have greatly increased the power requirements and the complexity of the power delivery scheme. The breakdown in Dennard scaling in the mid-2000s has ushered in the multicore era which has increased the number of cores and the power consumption in microprocessors. The steady growth in the power levels and the number of power rails in high-performance microprocessors have increased the power delivery challenges. Integrated voltage regulators (IVRs) have emerged as a key power delivery technology to address these challenges. There are a number of IVR schemes implemented on-die ranging from the simple power gate to fully integrated switching regulators. After covering the fundamentals of power delivery, this article discusses the pros and cons of different types of IVR as well as the technology ingredients required to meet future IVR requirements. This article concludes with a section on advanced packaging technologies that are being developed and needed to enable heterogeneous integration and their impact on power delivery.

I. Introduction

Microprocessors have undergone a significant evolution in complexity and capability from their introduction in the early 1970s to the present day. The exponential increase in microprocessor performance and affordability can be attributed to the semiconductor industry’s adherence to Moore’s law which posits that the transistor count in a chip will double every two years [1]. Robert Dennard proposed a set of MOSFET scaling guidelines [2] that would enable transistors to achieve improved performance while reducing area and power. The traditional scaling approach as described by Dennard was very effective until the early 2000s in keeping the power density constant even as the transistors got progressively smaller each generation. However, as the gate oxide thickness scaled down to a handful of atomic layers, subthreshold leakage due to electron tunneling through the oxide has become an appreciable fraction of the overall dynamic current. As a result, process engineers had to resort to alternate methods through innovations in materials and transistor structure [3] to achieve the necessary area scaling to keep pace with Moore’s law. This can be inferred from Fig. 1 which plots the scaling trends for some key microprocessor metrics for the past fifty years [4]. While the nontraditional scaling methods have been mostly successful in scaling the transistor area while improving performance, they were not as effective in reducing power. Fig. 1.

Scaling trends for some key microprocessor metrics.