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SWEEP: Adaptive Task Scheduling for Exploring Energy Performance Trade-offs
2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)
Year: 2024 | Conference Paper |
Energy efficiency is becoming a major concern when running parallel computing systems owing to its impact on system reliability and operating cost. Recent works, that focus on energy efficient execution of task-based parallel applications on multi-core systems, leverage a subset of architectural features (core asymmetry, CPU DVFS and memory DVFS) and application attributes (inter-task parallelism,...Show More
STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures
Jing Chen;Madhavan Manivannan;Bhavishya Goel;Mustafa Abduljabbar;Miquel Pericàs
2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)
Year: 2022 | Conference Paper |
Cited by: Papers (1)
Reducing the energy consumption of parallel applications is becoming increasingly important. Current chip multiprocessors (CMPs) incorporate asymmetric cores (i.e. static asymmetry) and DVFS (i.e. dynamic asymmetry) to enable energy efficient execution. To reduce cost and complexity, designs typically organize asymmetric cores into core-clusters supporting the same DVFS setting across cores in a c...Show More
A Methodology for Modeling Dynamic and Static Power Consumption for Multicore Processors
2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS)
Year: 2016 | Conference Paper |
Cited by: Papers (26)
System designers and application programmersmust consider trade-offs between performance and energy. Making energy-aware decisions when designing an application or runtime system requires quantitative information about power consumed by different processor components. We present a methodology to model static and dynamic power consumption of individual cores and the uncore components, and we valida...Show More
Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell
Bhavishya Goel;Ruben Titos-Gil;Anurag Negi;Sally A. McKee;Per Stenstrom
2014 IEEE 28th International Parallel and Distributed Processing Symposium
Year: 2014 | Conference Paper |
Hardware transactional memory implementations are becoming increasingly available. For instance, the Intel Core i7 4770 implements Restricted Transactional Memory (RTM) support for Intel Transactional Synchronization Extensions (TSX). In this paper, we present a detailed evaluation of RTM performance and energy expenditure. We compare RTM behavior to that of the TinySTM software transactional memo...Show More
Embedded reconfigurable computing: the ERA approach
Georgios Keramidas;Stephan Wong;Fakhar Anjam;Anthony Brandon;Roel Seedorf;Claudio Scordino;Luigi Carro;Debora Matos;Roberto Giorgi;Stamatis Kavvadias;Sally A. Mckee;Bhavishya Goel;Vasileios Spiliopoulos
2013 11th IEEE International Conference on Industrial Informatics (INDIN)
Year: 2013 | Conference Paper |
The growing complexity and diversity of embedded systems-combined with continuing demands for higher performance and lower power consumption-places increasing pressure on embedded platforms designers. The target of the ERA project is to offer a holistic, multi-dimensional methodology to address these problems in a unified framework exploiting the inter- and intra-synergism between the reconfigurab...Show More
Power-Aware Resource Scheduling in Base Stations
Magnus Sjalander;Sally A. McKee;Bhavishya Goel;Peter Brauer;David Engdal;Andràs Vajda
2011 IEEE 19th Annual International Symposium on Modelling, Analysis, and Simulation of Computer and Telecommunication Systems
Year: 2011 | Conference Paper |
Cited by: Papers (1)
Base band stations for Long Term Evolution (LTE) communication processing tend to rely on over-provisioned resources to ensure that peak demands can be met. These systems must meet user Quality of Service expectations, but during non-peak workloads, for instance, many of the cores could be placed in low-power modes. One key property of such application-specific systems is that they execute frequen...Show More
Portable, scalable, per-core power estimation for intelligent resource management
Bhavishya Goel;Sally A. McKee;Roberto Gioiosa;Karan Singh;Major Bhadauria;Marco Cesati
Performance, power, and temperature are now all first-order design constraints. Balancing power efficiency, thermal constraints, and performance requires some means to convey data about real-time power consumption and temperature to intelligent resource managers. Resource managers can use this information to meet performance goals, maintain power budgets, and obey thermal constraints. Unfortunatel...Show More
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