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Rajesh Pamula - IEEE Xplore Author Profile

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Author details

Rajesh Pamula

Publications

9

Citations

92

Publications by Year

20182021

Co-Authors:

Armin AlaghiAkshat BooraKeith A. BowmanLuis CezeYidong Chen

Show All Co-Authors (24)

Rajesh Pamula

Affiliation

Skyworks

Publication Topics

Test Chip,
65-nm CMOS,
Guard Band,
Marginal Reduction,
Supply Voltage,
Time-to-digital Converter,
Transient Response,
Active Switches,
Adaptive Clocking,
Critical Path,
Fast Fourier Transform,
Load Current

Biography

Rajesh Pamula (M’15) received the B.Tech. degree in electrical engineering from IIT (BHU) Varanasi, Varanasi, India, in 2007, and the M.Sc. degree in electrical and electronics engineering from Imperial College London, London, U.K., in 2010.,From 2013 to 2017, he worked as a Research Assistant at MICAS/ESAT, KU Leuven, Leuven, Belgium, in collaboration with imec. He currently works as a Visiting Research Scientist at the Processing Systems Lab (PSyLab), University of Washington, Seattle, WA, USA. His research interests include biomedical circuits, low-power sensor circuit design, and hardware security circuits.,Mr. Pamula received the four Gold Medals by IIT (BHU) Varanasi in 2007, and the Analog Devices Outstanding Student Designer Award i...

Publications

9

Citations

92

Publications by Year

20182021

Co-Authors:

Armin Alaghi
Akshat Boora
Keith A. Bowman
Luis Ceze
Yidong Chen

Show All Co-Authors (24)

Author's Published Works

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Showing 1-9 of 9 results

Conferences (6)

Journals (3)

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Single Year
Rajesh Pamula(9)
Visvesh S. Sathe(5)
Xun Sun(4)
Visvesh Sathe(3)
Fahim ur Rahman(3)
University of Washington, Seattle, WA(5)
University of Washington, Seattle, WA, USA(2)
Department of Electrical and Computer Engineering, University of Washington, Seattle, USA(1)
Medtronic Inc.(1)
University of Washington(1)
2020 IEEE Symposium on VLSI Circuits(2)
IEEE Journal of Solid-State Circuits(2)
2018 IEEE Symposium on VLSI Circuits(1)
2019 IEEE International Solid-State Circuits Conference - (ISSCC)(1)
2021 IEEE Custom Integrated Circuits Conference (CICC)(1)
IEEE(9)
Honolulu, HI, USA(3)
San Francisco, CA, USA(2)
Austin, TX, USA(1)
Test Chip(6)
65-nm CMOS(5)
Time-to-digital Converter(4)
Guard Band(3)
Marginal Reduction(3)

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A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation

Arindam Mandal;Diego Peña;Rajesh Pamula;Karam Khateeb;Logan Murphy;Azadeh Yazdan-Shahmorad;Steve Perlmutter;Forrest Pape;Jacques C. Rudell;Visvesh Sathe

2021 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2021 | Conference Paper |

Cited by: Papers (3)

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Neural implants for closed-loop therapeutic neuromodulation - recording, processing, and delivering state and activity dependent neural stimulation to targeted regions of interest (ROIs) in the brain - are emerging as critical enablers of ground-breaking treatments of a wide range of neurological diseases and disorders. While existing systems deliver electrical stimulation by placing electrodes in...Show More

A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation

Arindam Mandal;Diego Peña;Rajesh Pamula;Karam Khateeb;Logan Murphy;Azadeh Yazdan-Shahmorad;Steve Perlmutter;Forrest Pape;Jacques C. Rudell;Visvesh Sathe

2021 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2021 | Conference Paper |

29.7 A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS

Chi-Hsiang Huang;Xun Sun;Yidong Chen;Rajesh Pamula;Arindam Mandal;Visvesh Sathe

2021 IEEE International Solid-State Circuits Conference (ISSCC)

Year: 2021 | Conference Paper |

Cited by: Papers (11)

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Single-inductor multiple-output (SIMO) converters present a promising technology for enabling fine-grained supply-voltage (Vdd) domains in SoCs. With efficiencies approaching those of buck converters, SIMO converters allow multiple domains to share a single inductor, thus reducing the use of bulky passive components [1-5]. However, SIMO converters suffer from a poor transient response and signific...Show More

29.7 A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS

Chi-Hsiang Huang;Xun Sun;Yidong Chen;Rajesh Pamula;Arindam Mandal;Visvesh Sathe

2021 IEEE International Solid-State Circuits Conference (ISSCC)

Year: 2021 | Volume: 64 | Conference Paper |

UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS

Xun Sun;Akshat Boora;Rajesh Pamula;Chi-Hsiang Huang;Diego Peña-Colaiocco;Visvesh S. Sathe

2020 IEEE Symposium on VLSI Circuits

Year: 2020 | Conference Paper |

Cited by: Papers (4)

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A new and improved Unified Clock and Power (UniCaP) architecture relies on dual-path feedback to further reduce supply-voltage (Vdd) margins in an ARM Cortex M0 processor while minimizing both peak cycle loss (Δφmax) and cycle-loss recovery time (Trecovery) associated with adaptive clocking. Measurements on a 65nm test chip demonstrate 91-99% Vdd margin reduction and 38X Trecovery improvement over...Show More

UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS

Xun Sun;Akshat Boora;Rajesh Pamula;Chi-Hsiang Huang;Diego Peña-Colaiocco;Visvesh S. Sathe

2020 IEEE Symposium on VLSI Circuits

Year: 2020 | Conference Paper |

Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS

Xun Sun;Akshat Boora;Rajesh Pamula;Chi-Hsiang Huang;Diego Peña-Colaiocco;Visvesh S. Sathe

2020 IEEE Symposium on VLSI Circuits

Year: 2020 | Conference Paper |

Cited by: Papers (1)

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This paper describes a digital control architecture for integrated voltage regulators (IVRs) that achieves time-optimal transient supply-voltage (Vdd) response under random load-current (Iload) fluctuation. Implementing low-complexity low-latency Model Predictive Control (MPC) is key to achieving a measured 2.49X settling-time (τsettle) improvement over optimally tuned Proportional Integral Differ...Show More

Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS

Xun Sun;Akshat Boora;Rajesh Pamula;Chi-Hsiang Huang;Diego Peña-Colaiocco;Visvesh S. Sathe

2020 IEEE Symposium on VLSI Circuits

Year: 2020 | Conference Paper |

Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS

Fahim ur Rahman;Rajesh Pamula;Visvesh S. Sathe

IEEE Journal of Solid-State Circuits

Year: 2020 | Volume: 55, Issue: 2 | Journal Article |

Cited by: Papers (5)

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This article describes an architecture that auto- nomously sets the operating supply voltage ( $V_{dd}$ ) of a digital system for minimum total energy dissipation, inclusive of regulator loss. The technique directly computes the energy per cycle (EPC) delivered by the supply to the system, to guide $V_{dd}$ adjustment for minimum energy-per-cycle point (MEP; voltage: $V_{MEP}$ and frequency: ...Show More

Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS

Fahim ur Rahman;Rajesh Pamula;Visvesh S. Sathe

IEEE Journal of Solid-State Circuits

Year: 2020 | Volume: 55, Issue: 2 | Journal Article |

19.1 Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS

Fahim ur Rahman;Rajesh Pamula;Akshat Boora;Xun Sun;Visvesh Sathe

2019 IEEE International Solid-State Circuits Conference - (ISSCC)

Year: 2019 | Conference Paper |

Cited by: Papers (6)

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Integrated circuits for ultra-low-power applications strive to minimize total system energy, while satisfying performance requirements. The supply voltage ($V_{dd}$) can be set to a Minimum Energy Point (MEP) [1, 2], where leakage and dynamic energy are suitably balanced. However, controlling operating frequency ($f_{c/k}$), while concurrently tracking a MEP sensitive to PVT and switching activity...Show More

19.1 Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS

Fahim ur Rahman;Rajesh Pamula;Akshat Boora;Xun Sun;Visvesh Sathe

2019 IEEE International Solid-State Circuits Conference - (ISSCC)

Year: 2019 | Conference Paper |

A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains

Fahim ur Rahman;Sung Kim;Naveen John;Roshan Kumar;Xi Li;Rajesh Pamula;Keith A. Bowman;Visvesh S. Sathe

IEEE Journal of Solid-State Circuits

Year: 2019 | Volume: 54, Issue: 4 | Journal Article |

Cited by: Papers (27)

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Correctly operating digital SoC domains at their target frequencies require the addition of supply voltage ( $V_{\mathrm{ dd}}$ ) guardbands to account for supply droop events and temperature variation. These guardbands degrade processor energy efficiency, especially in low-voltage sensor and IoT applications due to increased delay sensitivity to temperature and $V_{\mathrm{ dd}}$ variation. In ...Show More

A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains

Fahim ur Rahman;Sung Kim;Naveen John;Roshan Kumar;Xi Li;Rajesh Pamula;Keith A. Bowman;Visvesh S. Sathe

IEEE Journal of Solid-State Circuits

Year: 2019 | Volume: 54, Issue: 4 | Journal Article |

An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor

Fahim Ur Rahman;Sung Kim;Naveen John;Roshan Kumar;Xi Li;Rajesh Pamula;Keith A. Bowman;Visvesh. S. Sathe

2018 IEEE Symposium on VLSI Circuits

Year: 2018 | Conference Paper |

Cited by: Papers (8)

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An all-digital switched-capacitor (SC) based clock frequency (Felk) and supply voltage (V dd) regulator unifies Fclk and Vdd generation into a single control loop to reduce the V dd margin for variations in a sub-threshold ARM Cortex M0 processor. This fully-integrated unified clock and power (Uni-CaP) architecture allows continuous Vdd scalability without a low-dropout (LDO) regulator. Measuremen...Show More

An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor

Fahim Ur Rahman;Sung Kim;Naveen John;Roshan Kumar;Xi Li;Rajesh Pamula;Keith A. Bowman;Visvesh. S. Sathe

2018 IEEE Symposium on VLSI Circuits

Year: 2018 | Conference Paper |

Architecture Considerations for Stochastic Computing Accelerators

Vincent T. Lee;Armin Alaghi;Rajesh Pamula;Visvesh S. Sathe;Luis Ceze;Mark Oskin

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2018 | Volume: 37, Issue: 11 | Journal Article |

Cited by: Papers (27)

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Stochastic computing (SC) is an alternative computing technique for embedded systems which offers lower area and power, and better error resilience compared to binary-encoded (BE) computation. However, the potential of and general design methodologies for SC in accelerator architectures are not well-understood. In this paper, we evaluate individual SC operations, and end-to-end accelerator archite...Show More

Architecture Considerations for Stochastic Computing Accelerators

Vincent T. Lee;Armin Alaghi;Rajesh Pamula;Visvesh S. Sathe;Luis Ceze;Mark Oskin

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2018 | Volume: 37, Issue: 11 | Journal Article |

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