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Xun Sun

Publications
11
Citations
127
Publications by Year
20172022
Co-Authors:
Show All Co-Authors (19)
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Xun Sun

Affiliation

Department of Electrical and Computer Engineering
University of Washington
Seattle, WA, USA

Publication Topics

Biography

Xun Sun (Graduate Student Member, IEEE) received the B.S. degrees in electrical engineering from the University of Michigan, Ann Arbor, MI, USA, and from Shanghai Jiao Tong University, Shanghai, China, in 2016. She is currently pursuing the Ph.D. degree in electrical engineering with the University of Washington, Seattle, WA, USA.,She is a member of the Processing Systems Lab (PSyLab), University of Washington. Her research interests include integrated power converters, low-power mixed-signal circuits, and the application of control ideas to power-management problems.,Ms. Sun was a recipient of the Analog Device Outstanding Designer Award and interned with Intel Corporation, Hillsboro, OR, USA, in 2017.(Based on document published on 12 August 2021).
Publications
11
Citations
127
Publications by Year
20172022
Co-Authors:
Show All Co-Authors (19)
Author's Published Works

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Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control

Chi-Hsiang Huang;Yidong Chen;Xun Sun;Arindam Mandal;Venkata Rajesh Pamula;Nasser Kurd;Visvesh S. Sathe

IEEE Journal of Solid-State Circuits
Year: 2022 | Volume: 57, Issue: 1 | Journal Article |
Cited by: Papers (6)
Single-inductor multiple-output (SIMO) voltage regulators allow multiple voltage domains to share a single inductor, thus representing a domain-scalable approach to energy-efficient integrated voltage regulation (IVR). However, poor transient response and significant supply voltage ( ${V_{{\mathrm {dd}}}}$ ) ripple in SIMO regulators induce severe voltage margins. This article quantifies the prohi...Show More

Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control

Chi-Hsiang Huang;Yidong Chen;Xun Sun;Arindam Mandal;Venkata Rajesh Pamula;Nasser Kurd;Visvesh S. Sathe

Year: 2022 | Volume: 57, Issue: 1 | Journal Article |

29.7 A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS

Chi-Hsiang Huang;Xun Sun;Yidong Chen;Rajesh Pamula;Arindam Mandal;Visvesh Sathe

2021 IEEE International Solid-State Circuits Conference (ISSCC)
Year: 2021 | Conference Paper |
Cited by: Papers (11)
Single-inductor multiple-output (SIMO) converters present a promising technology for enabling fine-grained supply-voltage (Vdd) domains in SoCs. With efficiencies approaching those of buck converters, SIMO converters allow multiple domains to share a single inductor, thus reducing the use of bulky passive components [1-5]. However, SIMO converters suffer from a poor transient response and signific...Show More

29.7 A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS

Chi-Hsiang Huang;Xun Sun;Yidong Chen;Rajesh Pamula;Arindam Mandal;Visvesh Sathe

Year: 2021 | Volume: 64 | Conference Paper |

UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS

Xun Sun;Akshat Boora;Rajesh Pamula;Chi-Hsiang Huang;Diego Peña-Colaiocco;Visvesh S. Sathe

2020 IEEE Symposium on VLSI Circuits
Year: 2020 | Conference Paper |
Cited by: Papers (4)
A new and improved Unified Clock and Power (UniCaP) architecture relies on dual-path feedback to further reduce supply-voltage (Vdd) margins in an ARM Cortex M0 processor while minimizing both peak cycle loss (Δφmax) and cycle-loss recovery time (Trecovery) associated with adaptive clocking. Measurements on a 65nm test chip demonstrate 91-99% Vdd margin reduction and 38X Trecovery improvement over...Show More

UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS

Xun Sun;Akshat Boora;Rajesh Pamula;Chi-Hsiang Huang;Diego Peña-Colaiocco;Visvesh S. Sathe

Year: 2020 | Conference Paper |

Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS

Xun Sun;Akshat Boora;Rajesh Pamula;Chi-Hsiang Huang;Diego Peña-Colaiocco;Visvesh S. Sathe

2020 IEEE Symposium on VLSI Circuits
Year: 2020 | Conference Paper |
Cited by: Papers (1)
This paper describes a digital control architecture for integrated voltage regulators (IVRs) that achieves time-optimal transient supply-voltage (Vdd) response under random load-current (Iload) fluctuation. Implementing low-complexity low-latency Model Predictive Control (MPC) is key to achieving a measured 2.49X settling-time (τsettle) improvement over optimally tuned Proportional Integral Differ...Show More

Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS

Xun Sun;Akshat Boora;Rajesh Pamula;Chi-Hsiang Huang;Diego Peña-Colaiocco;Visvesh S. Sathe

Year: 2020 | Conference Paper |

An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor

Xun Sun;Fahim ur Rahman;Venkata Rajesh Pamula;Sung Kim;Xi Li;Naveen John;Visvesh S. Sathe

IEEE Journal of Solid-State Circuits
Year: 2019 | Volume: 54, Issue: 11 | Journal Article |
Cited by: Papers (12)
Traditional digital systems employ independent loops to control supply voltage ( ${\mathit {V}}_{\text {dd}}$ ) and clock frequency ( $f_{\text {clk}}$ ). A clock regulation loop, for instance, a phase-locked loop (PLL), locks the system clock to a reference clock (REFCLK). Concurrently, a voltage regulation loop sets ${\mathit {V}}_{\text {dd}}$ to a target value under rapidly varying load curr...Show More

An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor

Xun Sun;Fahim ur Rahman;Venkata Rajesh Pamula;Sung Kim;Xi Li;Naveen John;Visvesh S. Sathe

Year: 2019 | Volume: 54, Issue: 11 | Journal Article |

14.5 A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS

Xun Sun;Akshat Boora;Wenbing Zhang;Venkata Rajesh Pamula;Visvesh Sathe

2019 IEEE International Solid-State Circuits Conference - (ISSCC)
Year: 2019 | Conference Paper |
Cited by: Papers (25)
Low-Dropout Regulators (LDOs) play an important role in enabling fine-grained supply-voltage domains for energy-efficient SoC design [1]. Digital LDOs are of particular interest due to integration and scalability advantages, but their transient response is slowed down by intrinsic limitations in sampled feedback systems. Design margins to ensure stability across worst-case PVT conditions further d...Show More

14.5 A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS

Xun Sun;Akshat Boora;Wenbing Zhang;Venkata Rajesh Pamula;Visvesh Sathe

Year: 2019 | Conference Paper |

19.1 Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS

Fahim ur Rahman;Rajesh Pamula;Akshat Boora;Xun Sun;Visvesh Sathe

2019 IEEE International Solid-State Circuits Conference - (ISSCC)
Year: 2019 | Conference Paper |
Cited by: Papers (6)
Integrated circuits for ultra-low-power applications strive to minimize total system energy, while satisfying performance requirements. The supply voltage ($V_{dd}$) can be set to a Minimum Energy Point (MEP) [1, 2], where leakage and dynamic energy are suitably balanced. However, controlling operating frequency ($f_{c/k}$), while concurrently tracking a MEP sensitive to PVT and switching activity...Show More

19.1 Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS

Fahim ur Rahman;Rajesh Pamula;Akshat Boora;Xun Sun;Visvesh Sathe

Year: 2019 | Conference Paper |

A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction

Venkata Rajesh Pamula;Xun Sun;Sung Min Kim;Fahim ur Rahman;Baosen Zhang;Visvesh S. Sathe

IEEE Solid-State Circuits Letters
Year: 2018 | Volume: 1, Issue: 12 | Journal Article |
Cited by: Papers (19)
This letter presents a highly digital, technology scalable, and energy-efficient cryptographic-quality true random number generator (TRNG). The proposed architecture presents a balanced approach to TRNG design, relying on a simpler, noncryptographic quality physical random number generator (phyRNG) combined with energy-efficient integrated post-processing to de-correlate and de-bias the phyRNG bit...Show More

A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction

Venkata Rajesh Pamula;Xun Sun;Sung Min Kim;Fahim ur Rahman;Baosen Zhang;Visvesh S. Sathe

Year: 2018 | Volume: 1, Issue: 12 | Journal Article |

An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS

V. Rajesh Pamula;Xun Sun;Sung Kim;Fahim ur Rahman;Baosen Zhang;Visvesh S. Sathe

2018 IEEE Symposium on VLSI Circuits
Year: 2018 | Conference Paper |
Cited by: Papers (27)
We present a robust, all-digital True Random Number Generator (TRNG) architecture that efficiently combines low-quality physical random number generators (PRNGs) with integrated de-correlation and de-biasing. A 65-nm CMOS TRNG test chip demonstrates NIST test-suite compliance across 0.5-1.0 V supply voltage $(V_{\text{dd}})$ and −20-100 °C, even with significant PRNG entropy $(H)$ degradation. The...Show More

An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS

V. Rajesh Pamula;Xun Sun;Sung Kim;Fahim ur Rahman;Baosen Zhang;Visvesh S. Sathe

Year: 2018 | Conference Paper |

A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor

Xun Sun;Sung Kim;Fahim ur Rahman;Venkata Rajesh Pamula;Xi Li;Naveen John;Visvesh S. Sathe

2018 IEEE International Solid-State Circuits Conference - (ISSCC)
Year: 2018 | Conference Paper |
Cited by: Papers (12)
Integrated Voltage Regulation (IVR) using buck converters enables efficient, fine-grained supply-voltage control in modern SoC domains [1]. However, existing IVR implementations face several challenges. As voltage domains continue to shrink, reduced per-domain decoupling capacitance requires rapid IVR transient response, leading to unfavorable efficiency and supply droop margin trade-offs. Additio...Show More

A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor

Xun Sun;Sung Kim;Fahim ur Rahman;Venkata Rajesh Pamula;Xi Li;Naveen John;Visvesh S. Sathe

Year: 2018 | Conference Paper |

A Side-Channel Attack Resistant AES with 500Mbps, 1.92pJ/Bit PVT Variation Tolerant True Random Number Generator

Yimai Peng;Haobo Zhao;Xun Sun;Chen Sun

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Year: 2017 | Conference Paper |
Cited by: Papers (4)
In this paper a side-channel-attack resistant AES system with a variation-tolerant true Random Number Generator (tRNG) is implemented using IBM 0.13μm CMOS technology. As the random source for the AES, a meta-stability based tRNG takes advantage of an all-digital self-calibration method to compensate Process-Voltage-Temperature (PVT) variations, and thus guarantees output with extremely high rando...Show More

A Side-Channel Attack Resistant AES with 500Mbps, 1.92pJ/Bit PVT Variation Tolerant True Random Number Generator

Yimai Peng;Haobo Zhao;Xun Sun;Chen Sun

Year: 2017 | Conference Paper |

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