Abstract:
The first ultrathin oxide-nitride (O-N) gate dielectrics with oxide equivalent thickness of less than 2 nm have been deposited and characterized in n-MOSFET's. The O-N ga...Show MoreMetadata
Abstract:
The first ultrathin oxide-nitride (O-N) gate dielectrics with oxide equivalent thickness of less than 2 nm have been deposited and characterized in n-MOSFET's. The O-N gates, deposited by remote plasma-enhanced CVD, demonstrate reduced gate leakage when compared with oxides of equivalent thickness while retaining comparable drive currents.
Published in: IEEE Electron Device Letters ( Volume: 19, Issue: 4, April 1998)
DOI: 10.1109/55.663529
Citations are not available for this document.
Cites in Patents (5)Patent Links Provided by 1790 Analytics
1.
Kim, Deok-kee; Divakaruni, Ramachandra; Radens, Carl J.; Park, Dae-Gyu, "SIMPLIFIED VERTICAL ARRAY DEVICE DRAM EDRAM INTEGRATION METHOD AND STRUCTURE"
Inventors:
Kim, Deok-kee; Divakaruni, Ramachandra; Radens, Carl J.; Park, Dae-Gyu
Abstract:
The present invention provides a semiconductor structure that includes an active wordline located above a semiconductor memory device and a passive wordline located adjacent to said active wordline and above an active area of a substrate. In accordance with the present invention, the passive wordline is separated from the active area by a pad nitride. The present invention also provides methods that are capable of forming the inventive semiconductor structure.
Assignee:
INTERNATIONAL BUSINESS MACHINES CORP
Filing Date:
08 April 2005
Grant Date:
03 February 2009
Patent Classes:
Current U.S. Class:
257302000, 257300000, 257301000, 257E27096, 438259000
Current International Class:
H01L0271080
2.
Lucovsky, Gerald, "METHODS OF FORMING BINARY NONCRYSTALLINE OXIDE ANALOGS OF SILICON DIOXIDE"
Inventors:
Lucovsky, Gerald
Abstract:
A non-crystalline oxide is represented by the formula: ABO 4 wherein A is an element selected from Group IIIA of the periodic table; and B is an element selected from Group VB of the periodic table.
Assignee:
NORTH CAROLINA STATE UNIVERSITY
Filing Date:
13 January 2003
Grant Date:
03 February 2004
Patent Classes:
Current U.S. Class:
438585000, 257E21010, 257E21192, 257E21193, 257E21279, 257E21281, 438591000
Current International Class:
H01L0213205000
3.
Tsujikawa, Shimpei; Yugami, Jiro; Mine, Toshiyuki; Ushiyama, Masahiro, "SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF"
Inventors:
Tsujikawa, Shimpei; Yugami, Jiro; Mine, Toshiyuki; Ushiyama, Masahiro
Abstract:
The present invention provides a MOS semiconductor device which enables gate leakage current reduction with a thinner gate dielectric film for higher speed, and a production method thereof. According to the present invention, a gate dielectric film 6 is made as follows: after forming a silicon nitride film 3 with a specified thickness, it is annealed in an oxidizing atmosphere to form silicon oxide 4 on the silicon nitride film 3 , then this silicon oxide 4 is completely removed by exposure to a dissolving liquid. As a result, at depths between 0.12 nm and 0.5 nm from the top surface of the silicon nitride film 3 in the gate dielectric film 6 whose main constituent elements are silicon, nitrogen and oxygen, the nitrogen concentration is higher than the oxygen concentration. This enables the use of a thinner gate dielectric film with silicon, nitrogen and oxygen as main constituent elements while at the same time realizing reduction in leakage currents.
Assignee:
HITACHI LTD
Filing Date:
29 June 2001
Grant Date:
02 December 2003
Patent Classes:
Current U.S. Class:
438287000, 438756000, 438792000
Current International Class:
H01L0213360000, H01L0213100000, H01L0213020000
4.
Lucovsky, Gerald, "BINARY NON CRYSTALLINE OXIDE ANALOGS OF SILICON DIOXIDE FOR USE IN GATE DIELECTRICS"
Inventors:
Lucovsky, Gerald
Abstract:
The invention generally relates to oxides that may be used in conjunction with integrated circuit devices. The oxides are non-crystalline. The oxides are represented by the formula: ABO 4 , wherein A is an element selected form Group IIIA of the periodic table; and B is an element selected form Group VB of the periodic table. The oxides may be employed in field effect transistors as tin gate insulating layers having high dielectric constants.
Assignee:
NORTH CAROLINA STATE UNIVERSITY
Filing Date:
05 November 1999
Grant Date:
22 April 2003
Patent Classes:
Current U.S. Class:
257410000, 257411000, 257E21010, 257E21192, 257E21193, 257E21279, 257E21281
Current International Class:
H01L0299400000
5.
Daniel, David W.; Pinello, Dianne G.; Chisholm, Michael F., "FABRICATION OF DIFFERENTIAL GATE OXIDE THICKNESSES ON A SINGLE INTEGRATED CIRCUIT CHIP"
Inventors:
Daniel, David W.; Pinello, Dianne G.; Chisholm, Michael F.
Abstract:
Techniques for fabricating integrated circuits having devices with gate oxides having different thicknesses and a high nitrogen content include forming the gate oxides at pressures at least as high as 2.0 atmospheres in an ambient of a nitrogen-containing gas. In one implementation, a substrate includes a first region for forming a first device having a gate oxide of a first thickness and a second region for forming a second device having a gate oxide of a second different thickness. A first oxynitride layer is formed on the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres. A portion of the first oxynitride layer is removed to expose a surface of the substrate on the second region. Subsequently, a second oxynitride is formed over the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres to form the first and second gate oxides. Respective gate electrodes are formed over the first and second gate oxides. The oxynitride gates can have a nitrogen content in a range of about 0.2 to about 2.0 percent which can prevent the diffusion of boron ions from the gate electrodes into the oxynitride gates, thereby improving device characteristics. The oxynitride gates of different thicknesses are suitable for high and low voltage devices on the same integrated circuit.
Assignee:
LSI LOGIC CORP
Filing Date:
18 December 1998
Grant Date:
22 May 2001
Patent Classes:
Current U.S. Class:
438275000, 257E21616, 257E21625, 438769000, 438775000, 438776000
Current International Class:
H01L0218234000
