Effects of Si channel orientation on MOSFET characteristics | IEEE Conference Publication | IEEE Xplore

Effects of Si channel orientation on MOSFET characteristics


Abstract:

The Si channel surface orientation dependence of electrical characteristics in ultra-thin EOT gate MOSFETs was reviewed. The excellent DC and RF performance were obtained...Show More

Abstract:

The Si channel surface orientation dependence of electrical characteristics in ultra-thin EOT gate MOSFETs was reviewed. The excellent DC and RF performance were obtained in ultra-thin SiO2 gate p-MOSFETs with (110) oriented Si channel. The properties and electrical characteristics in n- and p-MOSFETs with 2 – 6 degree tilted off-axis (110) channel were also reported. The transconductance of p-MOSFET with off-axis channel was significantly degraded compared with that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved compared with that of normal channel. The changes were larger than those observed in slightly off-axis (100) samples. The gate leakage current and 1/f noise in (110) samples were also sensitive to off-axis angle.
Date of Conference: 11-14 May 2008
Date Added to IEEE Xplore: 09 July 2008
ISBN Information:
Conference Location: Nis, Serbia and Montenegro
References is not available for this document.

I. Introduction

For high-speed logic applications, in order to realize high performance despite a low supply voltage, MOSFET scaling has been achieved continuously by means of various modifications in the scaling rules. Since the beginning of the 1990s, in view of the expected limitation of conventional CMOS downsizing, various new types of three-dimensional MOSFETs have been proposed [1]–[2]. These new types of MOSFETs have special features in the channel, which consists of various Si surfaces with different crystal orientations. It is known that channel carrier mobility is strongly dependent on Si surface orientation [3]–[4]. Considering the introduction of both n and p-MOSFETs with vertical channel, it is possible to select the best surface for n-and p-MOSFETs separately [5]–[6]. Recently, CMOS with (100) channel n-MOSFETs and (110) channel p-MOSFETs has begun to be used for high-end microprocessor products [7].

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References is not available for this document.