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1.5-nm gate oxide CMOS on [110] surface-oriented Si substrate | IEEE Journals & Magazine | IEEE Xplore

1.5-nm gate oxide CMOS on [110] surface-oriented Si substrate


Abstract:

The dc and RF analog characteristics of ultrathin gate oxide CMOS on [110] surface-oriented Si substrates were investigated for the first time. The transconductance of p-...Show More

Abstract:

The dc and RF analog characteristics of ultrathin gate oxide CMOS on [110] surface-oriented Si substrates were investigated for the first time. The transconductance of p-MOSFETs on [110] substrates is 1.9 times greater than that on [100] substrates even in gate oxides in the direct-tunneling regime. An extremely high cutoff frequency of 110 GHz was obtained in 0.11 /spl mu/m gate length p-MOSFETs with 1.5 nm gate oxides. This is the highest value ever obtained for p-channel Si MOSFETs at room temperature. Further, it was demonstrated that more than 100 GHz of cutoff frequency is realized both for n- and p-MOSFETs. Thus, using [110] substrates results in a better balance for n- and p-MOS performances. The SiO/sub 2/ film and SiO/sub 2//Si interface qualities on [110] substrates were also investigated. In this experiment, it was found that direct-tunneling gate leakage current and initial 1/f noise of MOSFETs on [110] substrates are larger than those on [100] substrates. The reliability regarding Negative Bias Temperature Instability (NBTI) for p-MOSFETs on [110] substrates was also inferior to that for [100] MOSFETs. However, with a high-k insulator or improvement of the SiO/sub 2/ film quality, high mobility of p-MOSFETs on [110] substrates will have a potential not only for digital applications but also for new RF analog circuits under low supply voltage.
Published in: IEEE Transactions on Electron Devices ( Volume: 50, Issue: 4, April 2003)
Page(s): 1001 - 1008
Date of Publication: 25 June 2003

ISSN Information:


I. Introduction

Recently, there has been remarkable progress in improving the high-frequency characteristics of small geometry MOSFETs [1]. The International Technology Roadmap for Semiconductors 2001 (ITRS'01) [2] predicts mixed signal products with 0.5–50 GHz application supply voltage of 1.8–1.0 V for the year 2010. However, for future RF analog circuits, low supply voltage operation is one of the most difficult issues to be resolved. New ideas will be required in order to achieve a breakthrough. At present, in general, only n-MOSFETs are used for the RF part in analog circuits, because the gain of p-MOSFETs is lower than that of n-MOSFETs. However, in future, if p-MOSFETs whose gain is almost equal to that of n-MOSFETs are developed, better RF circuits will be realized. For example, a CMOS up-converter based on a current-mode self-switching mixer has been proposed for the supply voltage of 1.0 V [3]. CMOS RF analog circuits would have some merits. Compared with NMOS circuits, an low noise amplifier (LNA) using both n- and p-MOSFETs will be realized with higher gain and lower current and a mixer can be composed with a lower supply voltage and smaller distortion. Moreover, in designing a circuit including p-MOSFETs, there ought to be greater flexibility for folded technology. Thus, for future RF analog circuits, p-MOSFETs are expected to be more important components than at present.

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