I. Introduction
According to the provisions of the ITRS 2005 [1], sub-10-nm channel-length FETs will be manufactured in year 2016 for the HP22 technology node, and 5-nm channel lengths will be required for the HP14 node in year 2020. At these extreme limits, thin-body SOI transistors have been shown to suffer severe short-channel effects (SCE) [2]. Therefore, new device architectures with multigate or gate-all-around configuration are being investigated in order to exploit the ultimate potential of the CMOS technology. This leads to the consideration of silicon-based nanowire (NW) FETs [3]. For such new structures, a preliminary simulation work is important to investigate their features and performance limits, provided that the essential physical effects are properly accounted for by means of sound numerical models [4]–[6].