I. INTRODUCTION
Due to the exploration of alternative solutions featuring high performances, nanoelectronic devices have evolved towards architectures allowing a much better electrostatics control of the device active region compared to conventional MOSFETs. GAA nanowires MOSFETs, regarding their particular shape, are one of the most promising architectures. This is due to the surface controlled by the surrounding gate which is significantly much higher than for planar devices. With this architecture (now considered as a realistic technology due to recent significant progress of technological processes [1], [2]), it is possible to envisage ultra-scaled devices as required by the International Technology Roadmap for Semiconductor (ITRS, [3]). In order to assess potentialities of such an architecture, a deep understanding is required from the electronic transport up to performances at the circuit level. Although theoretical papers already investigated nanowire transport, it is hardly to manage the physics up to circuit simulation. In this context, this paper focuses on the multi-subband electronic transport in nanowire for MOSFET application in order to provide brief analytical models to support simulation. In the following, we will concentrate on the electron mobility, and more particularly on the impact of diameter shrinking thanks to numerical investigation. Then, physics-based analytical model is provided up to the backscattering coefficient where the impact of diameter is assessed from a compact model point of view.