Band-Structure Effects in Ultrascaled Silicon Nanowires | IEEE Journals & Magazine | IEEE Xplore

Band-Structure Effects in Ultrascaled Silicon Nanowires


Abstract:

In this paper, we investigate band-structure effects on the transport properties of ultrascaled silicon nanowire FETs operating under quantum-ballistic conditions. More s...Show More

Abstract:

In this paper, we investigate band-structure effects on the transport properties of ultrascaled silicon nanowire FETs operating under quantum-ballistic conditions. More specifically, we expand the dispersion relationship epsiv(kappa) in a power series up to the third order in kappa2 and generate the corresponding higher order operator to be used within the single-electron Hamiltonian for the solution of the Schrodinger equation. We work out a hierarchy of nonparabolic models accounting for the following: 1) the shift of the subband edges and the change in the transport effective masses; 2) the higher order Hamiltonian operator; and 3) the splitting of the fourfold unprimed subbands in nanometer-size FETs. We then compute the device turn-on characteristics, the threshold shift versus diameter, and the subthreshold slope (SS) versus gate length. By compensating for the different threshold voltages, i.e., by reducing the turn- on characteristics to the same leakage current at zero gate bias, it turns out that the current discrepancies between the most general model and the bulk-parabolic model are contained within 20%. Finally, it turns out that the nonparabolic band structure gives an improved SS at the lowest gate lengths due to a reduced source-drain tunneling, reaching up to 30% enhancement.
Published in: IEEE Transactions on Electron Devices ( Volume: 54, Issue: 9, September 2007)
Page(s): 2243 - 2254
Date of Publication: 27 August 2007

ISSN Information:


I. Introduction

According to the provisions of the ITRS 2005 [1], sub-10-nm channel-length FETs will be manufactured in year 2016 for the HP22 technology node, and 5-nm channel lengths will be required for the HP14 node in year 2020. At these extreme limits, thin-body SOI transistors have been shown to suffer severe short-channel effects (SCE) [2]. Therefore, new device architectures with multigate or gate-all-around configuration are being investigated in order to exploit the ultimate potential of the CMOS technology. This leads to the consideration of silicon-based nanowire (NW) FETs [3]. For such new structures, a preliminary simulation work is important to investigate their features and performance limits, provided that the essential physical effects are properly accounted for by means of sound numerical models [4]–[6].

References

References is not available for this document.