Controller Hardware-In-the-Loop Validation of Phasor-Domain Algorithms for High-Speed Protection of Power Networks

Controller hardware-in-the-loop (CHIL) validation is a valuable technique that helps engineers develop, validate, and optimize control algorithms and controllers cost-effectively, efficiently, and safely. It plays a crucial role in developing and deploying advanced engineering systems across various industries. In this paper, the researchers have confirmed the effectiveness of four phasor domain algorithms for rapidly securing power networks on control hardware setups. This is accomplished by employing the TMS320F28335 prototype in a hardware-in-the-loop configuration. The performance of these algorithms is evaluated on a real-time digital simulator (RTDS), using a simulated 9-bus system.

I. Introduction

High-speed and reliable relaying for quick protection of power networks has been an interesting topic of research in the past several decades. The total fault-clearing time can be reduced by reducing the relay operating time and the breaker interrupting time. Only relay operating time is reduced by most of the phasor-domain sub-cycle or fast algorithms, such as [1] – [4], to reduce the total fault-clearing time. Sub-cycle-based algorithms are needed to achieve high-speed protection without compromising phasor accuracy. However, the decaying DC (DDC) component in fault current affects the phasor accuracy. Thus, sub-cycle methods, such as [1], [4], are needed to estimate DDC parameters and remove DDC from fault current. In addition, fast algorithms, such as [2], [3], are needed to detect and classify the fault and make the relays robust to power swings. In this paper, the CHIL validation of the above-mentioned four phasor-domain algorithms [1] – [4] for high-speed protection of power networks is conducted, and the obtained results are discussed. A brief background for the methods [1] – [4] is as follows.