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Bandi Ravi Kumar - IEEE Xplore Author Profile

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Controller hardware-in-the-loop (CHIL) validation is a valuable technique that helps engineers develop, validate, and optimize control algorithms and controllers cost-effectively, efficiently, and safely. It plays a crucial role in developing and deploying advanced engineering systems across various industries. In this paper, the researchers have confirmed the effectiveness of four phasor domain a...Show More
The estimation of decaying DC component (DDC) in fault currents plays a key role in transmission line protection. Several methods have been proposed in the literature to address the DDC problem. These methods can be broadly categorized into two categories: methods that filter DDC (category-I) and methods that estimate DDC (category-II). Among the second category methods, few methods have been prop...Show More
Sub-cycle algorithms aid in quick fault detection and isolation by digital relays. A new sub-cycle phase angle-based algorithm, to achieve 3 cycle Circuit Breaker (CB) operation, is proposed in this letter. Half-cycle DFT (HCDFT) is used to estimate the Instantaneous Phase Angles (IPAs) of the fundamental current and voltage. Modified IPAs (MIPAs) are derived from the IPAs. A Sub-Cycle Similarity ...Show More
Indian mathematician Srinivasa Ramanujan introduced a summation in 1918; now it is known as Ramanujan sum cq(n). For any fixed integer q, this is a sequence in n with periodicity q. In recent years, Ramanujan Sum has become a topic of interest in signal and image processing applications. But Ramanujan sum for power system applications is not explored by any power system researcher till date. In th...Show More
Accurate estimation of the fundamental phasors of voltage or current is a challenge to power system engineers. It becomes even more challenging when the decaying dc component (DDC) is present in the signal. This article proposes a sub-cycle-based algorithm for reducing the effect of DDC for accurate estimation of the phasor of fault current signal in the presence of odd harmonics and multiple DDCs...Show More
In this paper, a novel methodology for frequency estimation is proposed. It is based on a root-mean-squared combination of the two-point and three-point Interpolated Discrete Fourier Transform (IpDFT) with a rectangular window. The advantages of the proposed modified IpDFT are its short window length and high accuracy in frequency estimation as compared to the conventional two-point IpDFT and thre...Show More
A novel moving window phaselet based approach has been proposed in this paper for quick islanding detection (within 5-10ms) in ADNs, even in the case of zero power mismatch/ power balance case. The Instantaneous Phase Angle (IPA) and magnitude of the PCC voltage have been extracted through a linearly moving window phaselet to generate two indices - Phaselet Angle Difference (PAD) and Phaselet Magn...Show More
The phasor estimation of the fault current signal in the presence of dc offset results in the significant error, which is not suitable for the power system monitoring. To reduce the phasor estimation error of the fault current in the presence of dc offset, primarily the dc offset needs to be mitigated. In this letter, a four-sample method, which requires four sub-cycle samples as the input and est...Show More
A phaselet approach for the real-time differential protection of the series-shunt compensated transmission line is proposed here. Phasors of the signal using phaslet approach can be obtained at 0.4 sub cycle. The measured input currents from both ends of the transmission line are fed to the phasor estimation algorithm where both current signals are reconstructed by using the phaselet approach. An ...Show More