Hao Yu

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Gate-stack Optimization to Mitigate the Cylindrical Effect in Ferroelectric VNAND

Kwangsoo Kim;Suhwan Lim;Jongho Woo;Junyeong Lim;Sijung Yoo;Hyoseok Kim;Jaewoo Park;Haeyeon Jun;Seunghyun Kim;Myunghun Woo;Taeyoung Kim;Sanghyun Park;Hanseung Ko;Youngji Noh;Moonkang Choi;Jongyeon Baek;Jisung Kim;Kiheun Lee;Sam Park;Dukhyun Choe;Moonyoung Jung;Gukhyon Yon;Suhyeong Lee;Hyung Joon Kim;Kijoon Kim;Sungduk Hong;Kwangmin Park;Bong Jin Kuh;Wanki Kim;Daewon Ha;Sujin Ahn;Jaihyuk Song

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

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For the first time, we demonstrate an in-depth analysis on a novel multi-layered gate-interfacial-layer (G.IL) and high-k channel-interfacial-layer (Ch.IL) in metal-insulator-ferroelectric-insulator-silicon (MIFIS) gate stack FeFETs, using simulations and experimental validation. By exploring materials with varying energy barrier heights between the gate metal and G.IL to control the tunneling of ...Show More

Gate-stack Optimization to Mitigate the Cylindrical Effect in Ferroelectric VNAND

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

Highly manufacturable Self-Aigned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-dimensional Stacked FET at 48nm gate pitch

Jaehyun Park;Juhun Park;Kyuman Hwang;Jinchan Yun;Dahye Kim;Sungil Park;Jejune Park;Jinwook Yang;Jae Won Jeong;Chuljin Yun;Jinho Bae;Sam Park;Daihong Huh;Sanghyeon Kim;Seungeun Baek;Suk Yang;Inhae Zoh;Junghan Lee;Tae-sun Kim;Younsu Ha;Sun-Jung Lee;Sang Wuk Park;Bong Jin Kuh;Daewon Ha;Sangjin Hyun;Su Jin Ahn;Jaihyuk Song

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Year: 2024 | Conference Paper |

Cited by: Papers (4)

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In this study, we have demonstrated 3-Dimensional Stacked FET (3DSFET) with Self-Aligned Direct Back-side Contact (SA-DBC) and Back-side Gate Contact (BGC) in 48nm gate pitch, which is the smallest dimension and the world's first demonstration reported so far. Simultaneous threshold voltage

$(V_{t})$ targeting for both n- and pFET in common gate and n/p-connection with vertical common contact were...Show More

Highly manufacturable Self-Aigned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-dimensional Stacked FET at 48nm gate pitch

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Year: 2024 | Conference Paper |

Exploring Innovative IGZO-channel based DRAM Cell Architectures and Key Technologies for Sub-10nm Node

Daewon Ha;Y. Lee;S. Yoo;W. Lee;M. H. Cho;K. Yoo;S. M. Lee;S. Lee;M. Terai;T. H Lee;J. H. Bae;K. J. Moon;C. Sung;M. Hong;D. G. Cho;K. Lee;S.W. Park;K. Park;B. J. Kuh;S. Hyun;S. J. Ahn;J. H. Song

2024 IEEE International Memory Workshop (IMW)

Year: 2024 | Conference Paper |

Cited by: Papers (4)

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In order to sustain DRAM scaling trajectory below 10nm node, it is indispensable to adopt innovative cell structures, advanced processes and novel materials such as IGZO. In this paper, we will discuss promising candidates for IGZO-based DRAM cell architecture including vertical channel transistor (VCT), vertically stacked cell array transistor (VS-CAT) and capacitor-less two transistors (2T0C), a...Show More

Exploring Innovative IGZO-channel based DRAM Cell Architectures and Key Technologies for Sub-10nm Node

Daewon Ha;Y. Lee;S. Yoo;W. Lee;M. H. Cho;K. Yoo;S. M. Lee;S. Lee;M. Terai;T. H Lee;J. H. Bae;K. J. Moon;C. Sung;M. Hong;D. G. Cho;K. Lee;S.W. Park;K. Park;B. J. Kuh;S. Hyun;S. J. Ahn;J. H. Song

2024 IEEE International Memory Workshop (IMW)

Year: 2024 | Conference Paper |

First demonstration of 3-dimensional stacked FET with top/bottom source-drain isolation and stacked n/p metal gate

Jaehyun Park;Wukang Kim;Sungil Park;Jinchan Yun;Kyuman Hwang;Jinwook Yang;Dahye Kim;Jae Won Jeong;Chuljin Yun;Jinho Bae;Jejune Park;Sam Park;Woong Huh;Daihong Huh;Suk Yang;Junghan Lee;Jaehoon Seo;Ajeong Kim;Kyungseok Oh;Donggon Yoo;Bong Jin Kuh;Daewon Ha;Yu Gyun Shin;Jaihyuk Song

2023 International Electron Devices Meeting (IEDM)

Year: 2023 | Conference Paper |

Cited by: Papers (5)

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We report world’s first demonstration of n- and pMOSFET in 3-Dimensional Stacked FET (3DSFET) with vertically stacked n/p metal gate and isolated source/drain between top and bottom FETs. We proved the possibility of 3DSFET with respect to area scaling not only by vertically stacking but also by reducing gate pitch down to 45 nm, which is the smallest dimension reported so far in 3DSFETs. The elec...Show More

First demonstration of 3-dimensional stacked FET with top/bottom source-drain isolation and stacked n/p metal gate

2023 International Electron Devices Meeting (IEDM)

Year: 2023 | Conference Paper |

Highly Manufacturable, Cost-Effective, and Monolithically Stackable 4F2 Single-Gated IGZO Vertical Channel Transistor (VCT) for sub-10nm DRAM

Daewon Ha;Wonsok Lee;M.H. Cho;M. Terai;S.-W. Yoo;H. Kim;Y. Lee;S. Uhm;M. Ryu;C. Sung;Y. Song;K. Lee;S.W. Park;K.-S. Lee;Y.S. Tak;E. Hwang;J. Chae;C. Im;S. Byeon;M. Hong;K. Sim;W.J. Jung;H. Ryu;M.J. Hong;S. Park;J. Park;Y. Choi;S. Lee;G. Woo;J. Lee;D.S. Kim;B.J. Kuh;Yu Gyun Shin;Jaihyuk Song

2023 International Electron Devices Meeting (IEDM)

Year: 2023 | Conference Paper |

Cited by: Papers (5)

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For the first time, we demonstrated experimentally 4F2 single-gated IGZO-VCT, monolithically stacked on top of core/peripheral transistors without wafer bonding process for sub-10nm DRAM. Sufficiently low leakage current (IOFF) of <1 fA/cell, subthreshold swing (SS) of 164 mV/dec and VT of -1.73 V at 85°C is obtained with advanced processes. In order to achieve higher on-current (ION) and positive...Show More

Highly Manufacturable, Cost-Effective, and Monolithically Stackable 4F2 Single-Gated IGZO Vertical Channel Transistor (VCT) for sub-10nm DRAM

2023 International Electron Devices Meeting (IEDM)

Year: 2023 | Conference Paper |

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Showing 1-5 of 5 results

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Gate-stack Optimization to Mitigate the Cylindrical Effect in Ferroelectric VNAND

Gate-stack Optimization to Mitigate the Cylindrical Effect in Ferroelectric VNAND

Highly manufacturable Self-Aigned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-dimensional Stacked FET at 48nm gate pitch

Highly manufacturable Self-Aigned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-dimensional Stacked FET at 48nm gate pitch

Exploring Innovative IGZO-channel based DRAM Cell Architectures and Key Technologies for Sub-10nm Node

Exploring Innovative IGZO-channel based DRAM Cell Architectures and Key Technologies for Sub-10nm Node

First demonstration of 3-dimensional stacked FET with top/bottom source-drain isolation and stacked n/p metal gate

First demonstration of 3-dimensional stacked FET with top/bottom source-drain isolation and stacked n/p metal gate

Highly Manufacturable, Cost-Effective, and Monolithically Stackable 4F2 Single-Gated IGZO Vertical Channel Transistor (VCT) for sub-10nm DRAM

Highly Manufacturable, Cost-Effective, and Monolithically Stackable 4F2 Single-Gated IGZO Vertical Channel Transistor (VCT) for sub-10nm DRAM

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